From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1643) id 30102385801E; Mon, 10 Oct 2022 07:33:28 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 30102385801E DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1665387208; bh=upUmzHaXgwOXRvCa25nAqWBdrYSAsSkoT73sFqC+4P4=; h=From:To:Subject:Date:From; b=pMIJ56XKpZuRg2trrZ34aa2GsDxer9VTwrJVa/r8cna5x93r033cUBpKhPqDGn0Y+ VbwX3vIjO0X3yCunG3FaYEKAK+gxdL7VUgj5EPxAM7jpV2jiO/VwNRcIxCpESF6FRo 6vPmE/hkdivzYDABgq5PoT+1uoql2mVpj7Q9D97k= Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit From: Thomas Schwinge To: gcc-cvs@gcc.gnu.org Subject: [gcc/devel/rust/master] rust: Implement TARGET_RUST_CPU_INFO for i[34567]86-*-* and x86_64-*-* X-Act-Checkin: gcc X-Git-Author: Iain Buclaw X-Git-Refname: refs/heads/devel/rust/master X-Git-Oldrev: b220923f96344397c584245c09234a700b0ca243 X-Git-Newrev: f334e18a1f123357071684ee1b43477627c600d9 Message-Id: <20221010073328.30102385801E@sourceware.org> Date: Mon, 10 Oct 2022 07:33:28 +0000 (GMT) List-Id: https://gcc.gnu.org/g:f334e18a1f123357071684ee1b43477627c600d9 commit f334e18a1f123357071684ee1b43477627c600d9 Author: Iain Buclaw Date: Thu Sep 29 10:34:18 2022 +0200 rust: Implement TARGET_RUST_CPU_INFO for i[34567]86-*-* and x86_64-*-* There are still quite a lot of the previously reverted i386-rust.cc missing, so it's only a partial reimplementation. gcc/ChangeLog: * config/i386/t-i386 (i386-rust.o): New rule. * config/i386/i386-rust.cc: New file. * config/i386/i386-rust.h: New file. Diff: --- gcc/config/i386/i386-rust.cc | 129 +++++++++++++++++++++++++++++++++++++++++++ gcc/config/i386/i386-rust.h | 22 ++++++++ gcc/config/i386/t-i386 | 4 ++ 3 files changed, 155 insertions(+) diff --git a/gcc/config/i386/i386-rust.cc b/gcc/config/i386/i386-rust.cc new file mode 100644 index 00000000000..a00c4f8cee1 --- /dev/null +++ b/gcc/config/i386/i386-rust.cc @@ -0,0 +1,129 @@ +/* Subroutines for the Rust front end on the x86 architecture. + Copyright (C) 2022 Free Software Foundation, Inc. + +GCC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 3, or (at your option) +any later version. + +GCC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GCC; see the file COPYING3. If not see +. */ + +#define IN_TARGET_CODE 1 + +#include "config.h" +#include "system.h" +#include "coretypes.h" +#include "tm.h" +#include "tm_rust.h" +#include "rust/rust-target.h" + +/* Implement TARGET_RUST_CPU_INFO for x86 targets. */ + +void +ix86_rust_target_cpu_info (void) +{ + if (TARGET_64BIT) + rust_add_target_info ("target_arch", "x86_64"); + else + rust_add_target_info ("target_arch", "x86"); + + // features officially "stabilised" in rustc + if (TARGET_MMX) + rust_add_target_info ("target_feature", "mmx"); + if (TARGET_SSE) + rust_add_target_info ("target_feature", "sse"); + if (TARGET_SSE2) + rust_add_target_info ("target_feature", "sse2"); + if (TARGET_SSE3) + rust_add_target_info ("target_feature", "sse3"); + if (TARGET_SSSE3) + rust_add_target_info ("target_feature", "ssse3"); + if (TARGET_SSE4_1) + rust_add_target_info ("target_feature", "sse4.1"); + if (TARGET_SSE4_2) + rust_add_target_info ("target_feature", "sse4.2"); + if (TARGET_AES) + rust_add_target_info ("target_feature", "aes"); + if (TARGET_SHA) + rust_add_target_info ("target_feature", "sha"); + if (TARGET_AVX) + rust_add_target_info ("target_feature", "avx"); + if (TARGET_AVX2) + rust_add_target_info ("target_feature", "avx2"); + if (TARGET_AVX512F) + rust_add_target_info ("target_feature", "avx512f"); + if (TARGET_AVX512ER) + rust_add_target_info ("target_feature", "avx512er"); + if (TARGET_AVX512CD) + rust_add_target_info ("target_feature", "avx512cd"); + if (TARGET_AVX512PF) + rust_add_target_info ("target_feature", "avx512pf"); + if (TARGET_AVX512DQ) + rust_add_target_info ("target_feature", "avx512dq"); + if (TARGET_AVX512BW) + rust_add_target_info ("target_feature", "avx512bw"); + if (TARGET_AVX512VL) + rust_add_target_info ("target_feature", "avx512vl"); + if (TARGET_AVX512VBMI) + rust_add_target_info ("target_feature", "avx512vbmi"); + if (TARGET_AVX512IFMA) + rust_add_target_info ("target_feature", "avx512ifma"); + if (TARGET_AVX512VPOPCNTDQ) + rust_add_target_info ("target_feature", "avx512vpopcntdq"); + if (TARGET_FMA) + rust_add_target_info ("target_feature", "fma"); + if (TARGET_RTM) + rust_add_target_info ("target_feature", "rtm"); + if (TARGET_SSE4A) + rust_add_target_info ("target_feature", "sse4a"); + if (TARGET_BMI) + { + rust_add_target_info ("target_feature", "bmi1"); + rust_add_target_info ("target_feature", "bmi"); + } + if (TARGET_BMI2) + rust_add_target_info ("target_feature", "bmi2"); + if (TARGET_LZCNT) + rust_add_target_info ("target_feature", "lzcnt"); + if (TARGET_TBM) + rust_add_target_info ("target_feature", "tbm"); + if (TARGET_POPCNT) + rust_add_target_info ("target_feature", "popcnt"); + if (TARGET_RDRND) + { + rust_add_target_info ("target_feature", "rdrand"); + rust_add_target_info ("target_feature", "rdrnd"); + } + if (TARGET_F16C) + rust_add_target_info ("target_feature", "f16c"); + if (TARGET_RDSEED) + rust_add_target_info ("target_feature", "rdseed"); + if (TARGET_ADX) + rust_add_target_info ("target_feature", "adx"); + if (TARGET_FXSR) + rust_add_target_info ("target_feature", "fxsr"); + if (TARGET_XSAVE) + rust_add_target_info ("target_feature", "xsave"); + if (TARGET_XSAVEOPT) + rust_add_target_info ("target_feature", "xsaveopt"); + if (TARGET_XSAVEC) + rust_add_target_info ("target_feature", "xsavec"); + if (TARGET_XSAVES) + rust_add_target_info ("target_feature", "xsaves"); + if (TARGET_VPCLMULQDQ) + { + rust_add_target_info ("target_feature", "pclmulqdq"); + rust_add_target_info ("target_feature", "vpclmulqdq"); + } + if (TARGET_CMPXCHG16B) + rust_add_target_info ("target_feature", "cmpxchg16b"); + if (TARGET_MOVBE) + rust_add_target_info ("target_feature", "movbe"); +} diff --git a/gcc/config/i386/i386-rust.h b/gcc/config/i386/i386-rust.h new file mode 100644 index 00000000000..a837e2f1c74 --- /dev/null +++ b/gcc/config/i386/i386-rust.h @@ -0,0 +1,22 @@ +/* Definitions for the Rust front end on the x86 architecture. + Copyright (C) 2022 Free Software Foundation, Inc. + +GCC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 3, or (at your option) +any later version. + +GCC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GCC; see the file COPYING3. If not see +. */ + +/* In i386-rust.cc */ +extern void ix86_rust_target_cpu_info (void); + +/* Target CPU info for Rust. */ +#define TARGET_RUST_CPU_INFO ix86_rust_target_cpu_info diff --git a/gcc/config/i386/t-i386 b/gcc/config/i386/t-i386 index 4e2a0efc615..61ddfcab6ba 100644 --- a/gcc/config/i386/t-i386 +++ b/gcc/config/i386/t-i386 @@ -46,6 +46,10 @@ i386-d.o: $(srcdir)/config/i386/i386-d.cc $(COMPILE) $< $(POSTCOMPILE) +i386-rust.o: $(srcdir)/config/i386/i386-rust.cc + $(COMPILE) $< + $(POSTCOMPILE) + i386-options.o: $(srcdir)/config/i386/i386-options.cc $(COMPILE) $< $(POSTCOMPILE)