From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1005) id 35AED3858289; Mon, 10 Oct 2022 21:52:07 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 35AED3858289 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1665438728; bh=XyNEiOpE96icV0jRrxStKJ0EirZxhgkNPBH4mUE8mKU=; h=From:To:Subject:Date:From; b=mn5NvCtvSc3JcUgnwC73t1VCUTiikFAyYVxHSn+qwpUZmObUE4R+Nby4sCkivsLcy ohMsNaPwin6TwZDtmdlgXLZncdS2G05jBZnwmYSLjdPrf26wQya2aItTZ9yiaNtsMt EQXq5WFcxOOli4c+icluu95oT42dat74yDsKUil4= Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit From: Michael Meissner To: gcc-cvs@gcc.gnu.org Subject: [gcc(refs/users/meissner/heads/dmf001)] Update ChangeLog.meissner. X-Act-Checkin: gcc X-Git-Author: Michael Meissner X-Git-Refname: refs/users/meissner/heads/dmf001 X-Git-Oldrev: 4e378e5f0595acc7ecbf55e25e372a4b196560e9 X-Git-Newrev: e79b6684d4f2074fcfcb72d0010bb4c0789b77f8 Message-Id: <20221010215208.35AED3858289@sourceware.org> Date: Mon, 10 Oct 2022 21:52:07 +0000 (GMT) List-Id: https://gcc.gnu.org/g:e79b6684d4f2074fcfcb72d0010bb4c0789b77f8 commit e79b6684d4f2074fcfcb72d0010bb4c0789b77f8 Author: Michael Meissner Date: Mon Oct 10 17:51:42 2022 -0400 Update ChangeLog.meissner. 2022-10-10 Michael Meissner gcc/ * ChangeLog.meissner: Update. Diff: --- gcc/ChangeLog.meissner | 107 +++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 107 insertions(+) diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner index a0706e92964..dc19dd754a6 100644 --- a/gcc/ChangeLog.meissner +++ b/gcc/ChangeLog.meissner @@ -1,3 +1,110 @@ +==================== dmf001, patch #3 + +Add initial DMR register support for XOmode. + +2022-10-10 Michael Meissner + +gcc/ + + * config/rs6000/mma.md (movxo_p10): Rename from movxo, and limit its use + to non-DMF systems. + (movxo_dmf): New insn. + (mma_): NOP prime/de-prime usage when -mdmf is used. + * config/rs6000/rs6000.cc (rs6000_hard_regno_mode_ok_uncached): Allow + XOmode in DMR registers or Altivec registers if -mdmf. + (rs6000_setup_reg_addr_masks): Add support to allow TDOmode in DMF + registers, and also in Altivec registers if -mdmf. TDOmode registers + can do offset addressing but not indexed addressing. + (rs6000_init_hard_regno_mode_ok): Add support for TDOmode. + (reg_offset_addressing_ok_p): Likewise. + (rs6000_emit_move): Warn about using SUBREGs with TDOmode. + (rs6000_preferred_reload_class): DMF registers can't be loaded or + stored. With -mdmf, XOmode can go in Altivec registers. TDOmode needs + to use VSX registers for load/store. + (rs6000_compute_pressure_classes): Add DMF registers to the pressure + classses. + (rs6000_split_multireg_move): If -mdmf, we don't need to prime or + de-prime the acculators. Add initial support for TDOmode. + (rs6000_invalid_conversion): Warn about converting __dmr types. + * config/rs6000/rs6000.h (DMF_REG_CLASS_P): New macro. + +==================== dmf001, patch #2 + +Add initial DMR register support. + +2022-10-07 Michael Meissner + +gcc/ + + * config/rs6000/constraints.md (wD): New constraint. + * config/rs6000/predicates.md (dmf_operand): New predicate. + * config/rs6000/rs6000-modes.def (TDOmode): New opaque mode. + * config/rs6000/rs6000.cc (rs6000_reg_type): Add support for DMF + registers. + (rs6000_reload_reg_type): Likewise. + (LAST_RELOAD_REG_CLASS): Likewise. + (reload_reg_map): Likewise. + (addr_mask_type): Grow to 16 bits. + (RELOAD_REG_NO_MEMORY): New RELOAD_REG macro. + (rs6000_reg_names): Add DMR registers. + (alt_reg_names): Likewise. + (rs6000_hard_regno_nregs_internal): Add support for DMF registers. + (rs6000_hard_regno_mode_ok_uncached): Likewise. + (rs6000_modes_tieable_p): Likewise. + (rs6000_debug_addr_mask): Likewise. + (rs6000_debug_reg_global): Likewise. + (rs6000_setup_reg_addr_masks): Likewise. + (rs6000_init_hard_regno_mode_ok): Likewise. + * config/rs6000/rs6000.h (UNITS_PER_DMF_WORD): New macro. + (FIRST_PSEUDO_REGISTER): Add support for DMF registers. + (FIXED_REGISTERS): Likewise. + (CALL_REALLY_USED_REGISTERS): Likewise. + (REG_ALLOC_ORDER): Likewise. + (DMF_REGNO_P): New macro. + (enum reg_class): Likewise. + (REG_CLASS_NAMES): Likewise. + (REG_CLASS_CONTENTS): Likewise. + (REGISTER_NAMES): Likewise. + (ADDITIONAL_REGISTER_NAMES): Likewise. + * config/rs6000/rs6000.md (FIRST_DMF_REGNO): New constant. + (LAST_DMF_REGNO): New constant. + (isa attribute): Add dmf and mma_fpr attributes. + (enabled attribute): Add support for dmf and mma_fpr attributes. + +==================== dmf001, patch #3 + +Add -mcpu=future/-mdmf instrastructure. + +2022-10-07 Michael Meissner + +gcc/ + + * config/rs6000/rs6000-c.cc (rs6000_target_modify_macros): Define + __DMF__ if dmf support is enabled. + * config/rs6000/rs6000-cpus.def (ISA_FUTURE_MASKS): New macro. + (POWERPC_MASKS): Add -mblock-ops-vector-pair and -mdmf. + (future cpu): Add -mcpu=future and -mtune=future support. + * config/rs6000/rs6000-opts.h (processor_type): Add PROCESSOR_FUTURE. + * config/rs6000/rs6000-tables.op: Regenerate. + * config/rs6000/rs6000.cc (rs6000_option_override_internal): Add + -mcpu=future and -mtune=future support, but for now make them mostly + equivalent to power10. Add -mdmf checking. + (rs6000_machine_from_flags): Likewise. + (rs6000_reassociation_width): Likewise. + (rs6000_adjust_cost): Likewise. + (rs6000_issue_rate): Likewise. + (rs6000_sched_reorder): Likewise. + (rs6000_sched_reorder2): Likewise. + (rs6000_register_move_cost): Likewise. + (rs6000_opt_masks): Add -mdmf. + * config/rs6000/rs6000.h (ASM_CPU_SPEC): Add -mcpu=future support. + * config/rs6000/rs6000.md (cpu attribute): Add future. + (isa attribute): Add dmf. + (enabled attribute): Likewise. + * config/rs6000/rs6000.opt (-mdmf): New option. + +==================== dmf001, base line + 2022-10-06 Michael Meissner Clone branch