From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 2093) id 8D12E3858C2D; Tue, 11 Oct 2022 01:53:07 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 8D12E3858C2D DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1665453187; bh=RPjN/DAAFfxMUY+ve0y433gRo0GdqoSZjIPa1D6DrZg=; h=From:To:Subject:Date:From; b=YCq2oItNzjliB5DYTgEobPO2KEVZF12v06D6Dn10SqnSklIefBDklFq1wOebDi5SY gPaaPsNHTV4Dc1CVdV+bdpxpmPDbDcVi8v106d4Lagu4vw/t8ZvhFN0hjjg8isIAQH FIqltfxzrnb+TGPRyCwM22VLqwqYEK8U+kcI5YG0= MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="utf-8" From: Kito Cheng To: gcc-cvs@gcc.gnu.org Subject: [gcc r13-3209] RISC-V: Add missing vsetvl instruction type. X-Act-Checkin: gcc X-Git-Author: Ju-Zhe Zhong X-Git-Refname: refs/heads/master X-Git-Oldrev: 27bfe54e975d12aac750f0702f716a4c1c0a81fe X-Git-Newrev: 1627d05240da3b1a985b1b2006b7a9f562fe9d43 Message-Id: <20221011015307.8D12E3858C2D@sourceware.org> Date: Tue, 11 Oct 2022 01:53:07 +0000 (GMT) List-Id: https://gcc.gnu.org/g:1627d05240da3b1a985b1b2006b7a9f562fe9d43 commit r13-3209-g1627d05240da3b1a985b1b2006b7a9f562fe9d43 Author: Ju-Zhe Zhong Date: Mon Oct 10 21:43:22 2022 +0800 RISC-V: Add missing vsetvl instruction type. When implementing built-in framework, I notice I missed vsetvl instruction type, so add it in a single patch preparing for the following patches. gcc/ChangeLog: * config/riscv/riscv.md: Add vsetvl instruction type. Reviewed-by: Kito Cheng Diff: --- gcc/config/riscv/riscv.md | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md index 014206fb8bd..2d1cda2b98f 100644 --- a/gcc/config/riscv/riscv.md +++ b/gcc/config/riscv/riscv.md @@ -229,6 +229,7 @@ ;; Classification of RVV instructions which will be added to each RVV .md pattern and used by scheduler. ;; rdvlenb vector byte length vlenb csrr read ;; rdvl vector length vl csrr read +;; vsetvl vector configuration-setting instrucions ;; 7. Vector Loads and Stores ;; vlde vector unit-stride load instructions ;; vste vector unit-stride store instructions @@ -316,7 +317,7 @@ "unknown,branch,jump,call,load,fpload,store,fpstore, mtc,mfc,const,arith,logical,shift,slt,imul,idiv,move,fmove,fadd,fmul, fmadd,fdiv,fcmp,fcvt,fsqrt,multi,auipc,sfb_alu,nop,ghost,bitmanip,rotate, - rdvlenb,rdvl,vlde,vste,vldm,vstm,vlds,vsts, + rdvlenb,rdvl,vsetvl,vlde,vste,vldm,vstm,vlds,vsts, vldux,vldox,vstux,vstox,vldff,vldr,vstr, vialu,viwalu,vext,vicalu,vshift,vnshift,vicmp, vimul,vidiv,viwmul,vimuladd,viwmuladd,vimerge,vimov,