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From: Michael Meissner <meissner@gcc.gnu.org>
To: gcc-cvs@gcc.gnu.org
Subject: [gcc(refs/users/meissner/heads/dmf001)] Use MMA instruction instead of the renamed DMF instruction.
Date: Thu, 13 Oct 2022 17:58:28 +0000 (GMT) [thread overview]
Message-ID: <20221013175828.974BC385801C@sourceware.org> (raw)
https://gcc.gnu.org/g:36a68c5021e746a43b8a0ef76754bfc4040dea92
commit 36a68c5021e746a43b8a0ef76754bfc4040dea92
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Thu Oct 13 13:57:07 2022 -0400
Use MMA instruction instead of the renamed DMF instruction.
2022-10-13 Michael Meissner <meissner@linux.ibm.com>
gcc/
* config/rs6000/mma.md (vvi4i4i8_dmf): Delete.
(avvi4i4i8_dmf): Likewise.
(vvi4i4i2_dmf): Likewise.
(avvi4i4i2_dmf): Likewise.
(vvi4i4_dmf): Likewise.
(avvi4i4_dmf): Likewise.
(pvi4i2_dmf): Likewise.
(apvi4i2_dmf): Likewise.
(vvi4i4i4_dmf): Likewise.
(avvi4i4i4_dmf): Likewise.
(mma_<vv>): Use MMA instruction instead of the renamed DMF
instruction.
(mma_<avv>): Likewise.
(mma_<pv>): Likewise.
(mma_<apv>): Likewise.
(mma_<vvi4i4i8>): Likewise.
(mma_<avvi4i4i8>): Likewise.
(mma_<vvi4i4i2>): Likewise.
(mma_<avvi4i4i2>): Likewise.
(mma_<vvi4i4>): Likewise.
(mma_<avvi4i4>): Likewise.
(mma_<pvi4i2>): Likewise.
(mma_<apvi4i2>): Likewise.
(mma_<vvi4i4i4>): Likewise.
(mma_<avvi4i4i4>): Likewise.
* config/rs6000/rs6000.cc (print_operand): Rework %A error message.
Diff:
---
gcc/config/rs6000/mma.md | 110 ++++++--------------------------------------
gcc/config/rs6000/rs6000.cc | 2 +-
2 files changed, 15 insertions(+), 97 deletions(-)
diff --git a/gcc/config/rs6000/mma.md b/gcc/config/rs6000/mma.md
index 916e826d736..c0ac6addac9 100644
--- a/gcc/config/rs6000/mma.md
+++ b/gcc/config/rs6000/mma.md
@@ -227,22 +227,13 @@
(define_int_attr vvi4i4i8 [(UNSPEC_MMA_PMXVI4GER8 "pmxvi4ger8")])
-(define_int_attr vvi4i4i8_dmf [(UNSPEC_MMA_PMXVI4GER8 "pmdmxvi4ger8")])
-
(define_int_attr avvi4i4i8 [(UNSPEC_MMA_PMXVI4GER8PP "pmxvi4ger8pp")])
-(define_int_attr avvi4i4i8_dmf [(UNSPEC_MMA_PMXVI4GER8PP "pmdmxvi4ger8pp")])
-
(define_int_attr vvi4i4i2 [(UNSPEC_MMA_PMXVI16GER2 "pmxvi16ger2")
(UNSPEC_MMA_PMXVI16GER2S "pmxvi16ger2s")
(UNSPEC_MMA_PMXVF16GER2 "pmxvf16ger2")
(UNSPEC_MMA_PMXVBF16GER2 "pmxvbf16ger2")])
-(define_int_attr vvi4i4i2_dmf [(UNSPEC_MMA_PMXVI16GER2 "pmdmxvi16ger2")
- (UNSPEC_MMA_PMXVI16GER2S "pmdmxvi16ger2s")
- (UNSPEC_MMA_PMXVF16GER2 "pmdmxvf16ger2")
- (UNSPEC_MMA_PMXVBF16GER2 "pmdmxvbf16ger2")])
-
(define_int_attr avvi4i4i2 [(UNSPEC_MMA_PMXVI16GER2PP "pmxvi16ger2pp")
(UNSPEC_MMA_PMXVI16GER2SPP "pmxvi16ger2spp")
(UNSPEC_MMA_PMXVF16GER2PP "pmxvf16ger2pp")
@@ -254,56 +245,25 @@
(UNSPEC_MMA_PMXVBF16GER2NP "pmxvbf16ger2np")
(UNSPEC_MMA_PMXVBF16GER2NN "pmxvbf16ger2nn")])
-(define_int_attr avvi4i4i2_dmf [(UNSPEC_MMA_PMXVI16GER2PP "pmdmxvi16ger2pp")
- (UNSPEC_MMA_PMXVI16GER2SPP "pmdmxvi16ger2spp")
- (UNSPEC_MMA_PMXVF16GER2PP "pmdmxvf16ger2pp")
- (UNSPEC_MMA_PMXVF16GER2PN "pmdmxvf16ger2pn")
- (UNSPEC_MMA_PMXVF16GER2NP "pmdmxvf16ger2np")
- (UNSPEC_MMA_PMXVF16GER2NN "pmdmxvf16ger2nn")
- (UNSPEC_MMA_PMXVBF16GER2PP "pmdmxvbf16ger2pp")
- (UNSPEC_MMA_PMXVBF16GER2PN "pmdmxvbf16ger2pn")
- (UNSPEC_MMA_PMXVBF16GER2NP "pmdmxvbf16ger2np")
- (UNSPEC_MMA_PMXVBF16GER2NN "pmdmxvbf16ger2nn")])
-
(define_int_attr vvi4i4 [(UNSPEC_MMA_PMXVF32GER "pmxvf32ger")])
-(define_int_attr vvi4i4_dmf [(UNSPEC_MMA_PMXVF32GER "pmdmxvf32ger")])
-
(define_int_attr avvi4i4 [(UNSPEC_MMA_PMXVF32GERPP "pmxvf32gerpp")
(UNSPEC_MMA_PMXVF32GERPN "pmxvf32gerpn")
(UNSPEC_MMA_PMXVF32GERNP "pmxvf32gernp")
(UNSPEC_MMA_PMXVF32GERNN "pmxvf32gernn")])
-(define_int_attr avvi4i4_dmf [(UNSPEC_MMA_PMXVF32GERPP "pmdmxvf32gerpp")
- (UNSPEC_MMA_PMXVF32GERPN "pmdmxvf32gerpn")
- (UNSPEC_MMA_PMXVF32GERNP "pmdmxvf32gernp")
- (UNSPEC_MMA_PMXVF32GERNN "pmdmxvf32gernn")])
-
(define_int_attr pvi4i2 [(UNSPEC_MMA_PMXVF64GER "pmxvf64ger")])
-(define_int_attr pvi4i2_dmf [(UNSPEC_MMA_PMXVF64GER "pmdmxvf64ger")])
-
(define_int_attr apvi4i2 [(UNSPEC_MMA_PMXVF64GERPP "pmxvf64gerpp")
(UNSPEC_MMA_PMXVF64GERPN "pmxvf64gerpn")
(UNSPEC_MMA_PMXVF64GERNP "pmxvf64gernp")
(UNSPEC_MMA_PMXVF64GERNN "pmxvf64gernn")])
-(define_int_attr apvi4i2_dmf [(UNSPEC_MMA_PMXVF64GERPP "pmdmxvf64gerpp")
- (UNSPEC_MMA_PMXVF64GERPN "pmdmxvf64gerpn")
- (UNSPEC_MMA_PMXVF64GERNP "pmdmxvf64gernp")
- (UNSPEC_MMA_PMXVF64GERNN "pmdmxvf64gernn")])
-
(define_int_attr vvi4i4i4 [(UNSPEC_MMA_PMXVI8GER4 "pmxvi8ger4")])
-(define_int_attr vvi4i4i4_dmf [(UNSPEC_MMA_PMXVI8GER4 "pmdmxvi8ger4")])
-
(define_int_attr avvi4i4i4 [(UNSPEC_MMA_PMXVI8GER4PP "pmxvi8ger4pp")
(UNSPEC_MMA_PMXVI8GER4SPP "pmxvi8ger4spp")])
-(define_int_attr avvi4i4i4_dmf [(UNSPEC_MMA_PMXVI8GER4PP "pmdmxvi8ger4pp")
- (UNSPEC_MMA_PMXVI8GER4SPP "pmdmxvi8ger4spp")])
-
-
;; Vector pair support. OOmode can only live in VSRs.
(define_expand "movoo"
[(set (match_operand:OO 0 "nonimmediate_operand")
@@ -652,10 +612,7 @@
(match_operand:V16QI 2 "vsx_register_operand" "wa,v,?wa")]
MMA_VV))]
"TARGET_MMA"
- "@
- dm<vv> %0,%x1,%x2
- <vv> %A0,%x1,%x2
- <vv> %A0,%x1,%x2"
+ "<vv> %A0,%x1,%x2"
[(set_attr "type" "mma")
(set_attr "isa" "dmf,mma_fpr,mma_fpr")])
@@ -666,10 +623,7 @@
(match_operand:V16QI 3 "vsx_register_operand" "wa,v,?wa")]
MMA_AVV))]
"TARGET_MMA"
- "@
- dm<avv> %0,%x2,%x3
- <avv> %A0,%x2,%x3
- <avv> %A0,%x2,%x3"
+ "<avv> %A0,%x2,%x3"
[(set_attr "type" "mma")
(set_attr "isa" "dmf,mma_fpr,mma_fpr")])
@@ -679,10 +633,7 @@
(match_operand:V16QI 2 "vsx_register_operand" "wa,v,?wa")]
MMA_PV))]
"TARGET_MMA"
- "@
- dm<pv> %0,%x1,%x2
- <pv> %A0,%x1,%x2
- <pv> %A0,%x1,%x2"
+ "<pv> %A0,%x1,%x2"
[(set_attr "type" "mma")
(set_attr "isa" "dmf,mma_fpr,mma_fpr")])
@@ -693,10 +644,7 @@
(match_operand:V16QI 3 "vsx_register_operand" "wa,v,?wa")]
MMA_APV))]
"TARGET_MMA"
- "@
- dm<apv> %0,%x2,%x3
- <apv> %A0,%x2,%x3
- <apv> %A0,%x2,%x3"
+ "<apv> %A0,%x2,%x3"
[(set_attr "type" "mma")
(set_attr "isa" "dmf,mma_fpr,mma_fpr")])
@@ -709,10 +657,7 @@
(match_operand:SI 5 "u8bit_cint_operand" "n,n,n")]
MMA_VVI4I4I8))]
"TARGET_MMA"
- "@
- <vvi4i4i8_dmf> %0,%x1,%x2,%3,%4,%5
- <vvi4i4i8> %A0,%x1,%x2,%3,%4,%5
- <vvi4i4i8> %A0,%x1,%x2,%3,%4,%5"
+ "<vvi4i4i8> %A0,%x1,%x2,%3,%4,%5"
[(set_attr "type" "mma")
(set_attr "prefixed" "yes")])
@@ -726,10 +671,7 @@
(match_operand:SI 6 "u8bit_cint_operand" "n,n,n")]
MMA_AVVI4I4I8))]
"TARGET_MMA"
- "@
- <avvi4i4i8_dmf> %0,%x2,%x3,%4,%5,%6
- <avvi4i4i8> %A0,%x2,%x3,%4,%5,%6
- <avvi4i4i8> %A0,%x2,%x3,%4,%5,%6"
+ "<avvi4i4i8> %A0,%x2,%x3,%4,%5,%6"
[(set_attr "type" "mma")
(set_attr "prefixed" "yes")
(set_attr "isa" "dmf,mma_fpr,mma_fpr")])
@@ -743,10 +685,7 @@
(match_operand:SI 5 "const_0_to_3_operand" "n,n,n")]
MMA_VVI4I4I2))]
"TARGET_MMA"
- "@
- <vvi4i4i2_dmf> %0,%x1,%x2,%3,%4,%5
- <vvi4i4i2> %A0,%x1,%x2,%3,%4,%5
- <vvi4i4i2> %A0,%x1,%x2,%3,%4,%5"
+ "<vvi4i4i2> %A0,%x1,%x2,%3,%4,%5"
[(set_attr "type" "mma")
(set_attr "prefixed" "yes")
(set_attr "isa" "dmf,mma_fpr,mma_fpr")])
@@ -761,10 +700,7 @@
(match_operand:SI 6 "const_0_to_3_operand" "n,n,n")]
MMA_AVVI4I4I2))]
"TARGET_MMA"
- "@
- <avvi4i4i2_dmf> %0,%x2,%x3,%4,%5,%6
- <avvi4i4i2> %A0,%x2,%x3,%4,%5,%6
- <avvi4i4i2> %A0,%x2,%x3,%4,%5,%6"
+ "<avvi4i4i2> %A0,%x2,%x3,%4,%5,%6"
[(set_attr "type" "mma")
(set_attr "prefixed" "yes")
(set_attr "isa" "dmf,mma_fpr,mma_fpr")])
@@ -777,10 +713,7 @@
(match_operand:SI 4 "const_0_to_15_operand" "n,n,n")]
MMA_VVI4I4))]
"TARGET_MMA"
- "@
- <vvi4i4_dmf> %0,%x1,%x2,%3,%4
- <vvi4i4> %A0,%x1,%x2,%3,%4
- <vvi4i4> %A0,%x1,%x2,%3,%4"
+ "<vvi4i4> %A0,%x1,%x2,%3,%4"
[(set_attr "type" "mma")
(set_attr "prefixed" "yes")
(set_attr "isa" "dmf,mma_fpr,mma_fpr")])
@@ -794,10 +727,7 @@
(match_operand:SI 5 "const_0_to_15_operand" "n,n,n")]
MMA_AVVI4I4))]
"TARGET_MMA"
- "@
- <avvi4i4_dmf> %0,%x2,%x3,%4,%5
- <avvi4i4> %A0,%x2,%x3,%4,%5
- <avvi4i4> %A0,%x2,%x3,%4,%5"
+ "<avvi4i4> %A0,%x2,%x3,%4,%5"
[(set_attr "type" "mma")
(set_attr "prefixed" "yes")
(set_attr "isa" "dmf,mma_fpr,mma_fpr")])
@@ -810,10 +740,7 @@
(match_operand:SI 4 "const_0_to_3_operand" "n,n,n")]
MMA_PVI4I2))]
"TARGET_MMA"
- "@
- <pvi4i2_dmf> %0,%x1,%x2,%3,%4
- <pvi4i2> %A0,%x1,%x2,%3,%4
- <pvi4i2> %A0,%x1,%x2,%3,%4"
+ "<pvi4i2> %A0,%x1,%x2,%3,%4"
[(set_attr "type" "mma")
(set_attr "prefixed" "yes")
(set_attr "isa" "dmf,mma_fpr,mma_fpr")])
@@ -827,10 +754,7 @@
(match_operand:SI 5 "const_0_to_3_operand" "n,n,n")]
MMA_APVI4I2))]
"TARGET_MMA"
- "@
- <apvi4i2_dmf> %0,%x2,%x3,%4,%5
- <apvi4i2> %A0,%x2,%x3,%4,%5
- <apvi4i2> %A0,%x2,%x3,%4,%5"
+ "<apvi4i2> %A0,%x2,%x3,%4,%5"
[(set_attr "type" "mma")
(set_attr "prefixed" "yes")
(set_attr "isa" "dmf,mma_fpr,mma_fpr")])
@@ -844,10 +768,7 @@
(match_operand:SI 5 "const_0_to_15_operand" "n,n,n")]
MMA_VVI4I4I4))]
"TARGET_MMA"
- "@
- <vvi4i4i4_dmf> %0,%x1,%x2,%3,%4,%5
- <vvi4i4i4> %A0,%x1,%x2,%3,%4,%5
- <vvi4i4i4> %A0,%x1,%x2,%3,%4,%5"
+ "<vvi4i4i4> %A0,%x1,%x2,%3,%4,%5"
[(set_attr "type" "mma")
(set_attr "prefixed" "yes")
(set_attr "isa" "dmf,mma_fpr,mma_fpr")])
@@ -862,10 +783,7 @@
(match_operand:SI 6 "const_0_to_15_operand" "n,n,n")]
MMA_AVVI4I4I4))]
"TARGET_MMA"
- "@
- <avvi4i4i4_dmf> %0,%x2,%x3,%4,%5,%6
- <avvi4i4i4> %A0,%x2,%x3,%4,%5,%6
- <avvi4i4i4> %A0,%x2,%x3,%4,%5,%6"
+ "<avvi4i4i4> %A0,%x2,%x3,%4,%5,%6"
[(set_attr "type" "mma")
(set_attr "prefixed" "yes")
(set_attr "isa" "dmf,mma_fpr,mma_fpr")])
diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index b3e608dbaa4..d1a42d7ea5e 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -13920,7 +13920,7 @@ print_operand (FILE *file, rtx x, int code)
if (DMF_REGNO_P (REGNO (x)))
fprintf (file, "%d", REGNO (x) - FIRST_DMF_REGNO);
else
- output_operand_lossage ("%%A operand is not a DMF accumulator");
+ output_operand_lossage ("%%A operand is not a DMR");
}
else if (!FP_REGNO_P (REGNO (x)) || (REGNO (x) % 4) != 0)
output_operand_lossage ("invalid %%A value");
reply other threads:[~2022-10-13 17:58 UTC|newest]
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