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From: Michael Meissner <meissner@gcc.gnu.org> To: gcc-cvs@gcc.gnu.org Subject: [gcc(refs/users/meissner/heads/dmf001)] Update ChangeLog.meissner. Date: Fri, 14 Oct 2022 17:36:49 +0000 (GMT) [thread overview] Message-ID: <20221014173649.BF8D03858CDA@sourceware.org> (raw) https://gcc.gnu.org/g:fbea3374246c844d117848ac865fd12cc94fbd8b commit fbea3374246c844d117848ac865fd12cc94fbd8b Author: Michael Meissner <meissner@linux.ibm.com> Date: Fri Oct 14 13:36:29 2022 -0400 Update ChangeLog.meissner. 2022-10-14 Michael Meissner <meissner@linux.ibm.com> gcc/ * ChangeLog.meissner: Update. Diff: --- gcc/ChangeLog.meissner | 44 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 44 insertions(+) diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner index eb51fd476f3..11f48eb01fd 100644 --- a/gcc/ChangeLog.meissner +++ b/gcc/ChangeLog.meissner @@ -1,3 +1,47 @@ +==================== dmf001, patch #10 + +Make wD switch between FPRs and DMFs. + +2022-10-14 Michael Meissner <meissner@linux.ibm.com> + +gcc/ + + * constraints.md (wD): Change wD to be FPR registers for power10 and DMF + registers for DMF systems. + * config/rs6000/mma.md (vvi4i4i8_insn): New int attribute. + (avvi4i4i8_insn): Likewise. + (vvi4i4i2_insn): Likewise. + (avvi4i4i2_insn): Likewise. + (vvi4i4_insn): Likewise. + (avvi4i4_insn): Likewise. + (pvi4i2_insn): Likewise. + (apvi4i2_insn): Likewise. + (vvi4i4i4_insn): Likewise. + (avvi4i4i4_insn): Likewise. + (mma_<vv>): Use wD constraint for accumulator inputs and outputs. + (mma_<avv>): Likewise. + (mma_<pv>): Likewise. + (mma_<apv>): Likewise. + (mma_<vvi4i4i8>): Likewise. + (mma_<avvi4i4i8>): Likewise. + (mma_<vvi4i4i2): Likewise. + (mma_<avvi4i4i2>): Likewise. + (mma_<vvi4i4>): Likewise. + (mma_<avvi4i4>): Likewise. + (mma_<pvi4i2>): Likewise. + (mma_<apvi4i2>): Likewise. + (mma_<vvi4i4i4): Likewise. + (mma_<avvi4i4i4>): Likewise. + * config/rs6000/s6000.cc (rs6000_debug_reg_global): Print what register + class wD implements. + (rs6000_init_hard_regno_mode_ok): Set up to make wD constraint choose + DMF accumualators on DMF systems and FPR registers on MMA systems + without DMF. + (print_operand): Add %d<n> output modifier, to print 'dm' or nothing to + switch MMA instructions being generated. + * config/rs6000/rs6000.h (enum rs6000_reg_class_enum): Add wD option. + * doc/md.texi (PowerPC constraints): Document the wD constraint. + ==================== dmf001, patch #9 Use MMA instruction instead of the renamed DMF instruction.
next reply other threads:[~2022-10-14 17:36 UTC|newest] Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top 2022-10-14 17:36 Michael Meissner [this message] -- strict thread matches above, loose matches on Subject: below -- 2022-10-27 5:17 Michael Meissner 2022-10-27 3:37 Michael Meissner 2022-10-20 6:06 Michael Meissner 2022-10-20 4:11 Michael Meissner 2022-10-19 4:16 Michael Meissner 2022-10-19 3:53 Michael Meissner 2022-10-19 3:46 Michael Meissner 2022-10-18 22:36 Michael Meissner 2022-10-18 22:26 Michael Meissner 2022-10-17 23:18 Michael Meissner 2022-10-15 0:12 Michael Meissner 2022-10-15 0:06 Michael Meissner 2022-10-13 17:59 Michael Meissner 2022-10-12 2:33 Michael Meissner 2022-10-11 23:19 Michael Meissner 2022-10-11 16:02 Michael Meissner 2022-10-10 21:52 Michael Meissner 2022-10-10 21:52 Michael Meissner
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