From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1005) id E53103858D39; Tue, 18 Oct 2022 22:34:27 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org E53103858D39 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1666132467; bh=TUc2CmmecHiIQQQ2La7jnDu9E02FnBR1niQ29xzSaSs=; h=From:To:Subject:Date:From; b=Cdg11KmsyiyWw3V/ITfkYT4LaSCVwQATx6r1V+6ZTL1Gp7tDpdK/0F3DOomaQrMyi sLfRc9obMT/nbBDpwHOPZ9U53mlRqPnT0hTcB8I0gni6RN2oadb0yum6KBTlfZOSzF cBXpHK9XXGdoqXiEJODHxE2fs6giO0YP7+8VT1Ls= Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit From: Michael Meissner To: gcc-cvs@gcc.gnu.org Subject: [gcc(refs/users/meissner/heads/dmf001)] Update DMR move costs. X-Act-Checkin: gcc X-Git-Author: Michael Meissner X-Git-Refname: refs/users/meissner/heads/dmf001 X-Git-Oldrev: 8d8ffe7c3f4af8e68d365488367b32b40d503067 X-Git-Newrev: e17f0299aede2bb4c77aaa1d875365100ecafff5 Message-Id: <20221018223427.E53103858D39@sourceware.org> Date: Tue, 18 Oct 2022 22:34:27 +0000 (GMT) List-Id: https://gcc.gnu.org/g:e17f0299aede2bb4c77aaa1d875365100ecafff5 commit e17f0299aede2bb4c77aaa1d875365100ecafff5 Author: Michael Meissner Date: Tue Oct 18 18:34:10 2022 -0400 Update DMR move costs. 2022-10-18 Michael Meissner gcc/ * config/rs6000/rs6000.cc (rs6000_secondary_reload_memory): Account for extra instructions needed to load/store DMF registers using VSX registers. (rs6000_dmf_register_move_cost): New helper function. (rs6000_register_move_cost): Add costs for moving DMF registers. (rs6000_memory_move_cost): Add support for DMF registers. Diff: --- gcc/config/rs6000/rs6000.cc | 61 ++++++++++++++++++++++++++++++++++++++------- 1 file changed, 52 insertions(+), 9 deletions(-) diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc index c29cfd4ce50..9d5d1ce1930 100644 --- a/gcc/config/rs6000/rs6000.cc +++ b/gcc/config/rs6000/rs6000.cc @@ -12170,9 +12170,10 @@ rs6000_secondary_reload_memory (rtx addr, addr_mask = (reg_addr[mode].addr_mask[RELOAD_REG_VMX] & ~RELOAD_REG_AND_M16); - /* DMR registers don't support loads or stores. */ + /* DMR registers use VSX registers, and need to generate some extra + instructions. */ else if (rclass == DMF_REGS) - return -1; + return 2; /* If the register allocator hasn't made up its mind yet on the register class to use, settle on defaults to use. */ @@ -22563,6 +22564,35 @@ rs6000_debug_address_cost (rtx x, machine_mode mode, } +/* Subroutine to determine the move cost of DMF registers. If we are moving + to/from VSX_REGISTER registers, the cost is either 1 move (for 512-bit + accumulators) or 2 moves (for 1,024 dmr registers). If we are moving to + anything else like GPR registers, make the cost very high. */ + +static int +rs6000_dmf_register_move_cost (machine_mode mode, reg_class_t rclass) +{ + const int reg_move_base = 2; + HARD_REG_SET vsx_set = (reg_class_contents[rclass] + & reg_class_contents[VSX_REGS]); + + if (TARGET_DMF && !hard_reg_set_empty_p (vsx_set)) + { + /* __vector_quad (i.e. XOmode) is tranfered in 1 instruction. */ + if (mode == XOmode) + return reg_move_base; + + /* __dmr (i.e. TDOmode) is transferred in 2 instructions. */ + else if (mode == TDOmode) + return reg_move_base * 2; + + else + return reg_move_base * 2 * hard_regno_nregs (FIRST_DMF_REGNO, mode); + } + + return 1000 * 2 * hard_regno_nregs (FIRST_DMF_REGNO, mode); +} + /* A C expression returning the cost of moving data from a register of class CLASS1 to one of CLASS2. */ @@ -22576,17 +22606,28 @@ rs6000_register_move_cost (machine_mode mode, if (TARGET_DEBUG_COST) dbg_cost_ctrl++; + HARD_REG_SET to_vsx, from_vsx; + to_vsx = reg_class_contents[to] & reg_class_contents[VSX_REGS]; + from_vsx = reg_class_contents[from] & reg_class_contents[VSX_REGS]; + + /* Special case DMR registers, that can only move to/from VSX registers. */ + if (from == DMF_REGS && to == DMF_REGS) + ret = 2 * hard_regno_nregs (FIRST_DMF_REGNO, mode); + + else if (from == DMF_REGS) + ret = rs6000_dmf_register_move_cost (mode, to); + + else if (to == DMF_REGS) + ret = rs6000_dmf_register_move_cost (mode, from); + /* If we have VSX, we can easily move between FPR or Altivec registers, otherwise we can only easily move within classes. Do this first so we give best-case answers for union classes containing both gprs and vsx regs. */ - HARD_REG_SET to_vsx, from_vsx; - to_vsx = reg_class_contents[to] & reg_class_contents[VSX_REGS]; - from_vsx = reg_class_contents[from] & reg_class_contents[VSX_REGS]; - if (!hard_reg_set_empty_p (to_vsx) - && !hard_reg_set_empty_p (from_vsx) - && (TARGET_VSX - || hard_reg_set_intersect_p (to_vsx, from_vsx))) + else if (!hard_reg_set_empty_p (to_vsx) + && !hard_reg_set_empty_p (from_vsx) + && (TARGET_VSX + || hard_reg_set_intersect_p (to_vsx, from_vsx))) { int reg = FIRST_FPR_REGNO; if (TARGET_VSX @@ -22682,6 +22723,8 @@ rs6000_memory_move_cost (machine_mode mode, reg_class_t rclass, ret = 4 * hard_regno_nregs (32, mode); else if (reg_classes_intersect_p (rclass, ALTIVEC_REGS)) ret = 4 * hard_regno_nregs (FIRST_ALTIVEC_REGNO, mode); + else if (reg_classes_intersect_p (rclass, DMF_REGS)) + ret = 4 + rs6000_register_move_cost (mode, rclass, VSX_REGS); else ret = 4 + rs6000_register_move_cost (mode, rclass, GENERAL_REGS);