[gcc(refs/users/meissner/heads/dmf001)] Add -mlagen.

[Michael Meissner <meissner@gcc.gnu.org>]

https://gcc.gnu.org/g:ca75fd83ed750c612f0608050513c996e1d0efa6

commit ca75fd83ed750c612f0608050513c996e1d0efa6
Author: Michael Meissner <meissner@linux.ibm.com>
Date:   Wed Oct 19 21:16:47 2022 -0400

    Add -mlagen.
    
    2022-10-19   Michael Meissner  <meissner@linux.ibm.com>
    
    gcc/
    
            * config/rs6000/rs6000-cpus.def (POWERPC_MASKS): Add -mlagen.
            * config/rs6000/rs6000.cc (rs6000_file_start): Add macros for lagen.
            (rs6000_opt_masks): Add lagen.
            * config/rs6000/rs6000.md (lagendi3): New insn for -mlagen support.
            (plagendi3_nora): Likewise.
            (plagendi3): Likewise.
            (plagendi3_noshift): Likewise.
            * config/rs6000/rs6000.opt (-mlagen): New option.

Diff:
---
 gcc/config/rs6000/rs6000-cpus.def |  1 +
 gcc/config/rs6000/rs6000.cc       | 30 ++++++++++++++++++++++++++++
 gcc/config/rs6000/rs6000.md       | 42 +++++++++++++++++++++++++++++++++++++++
 gcc/config/rs6000/rs6000.opt      |  4 ++++
 4 files changed, 77 insertions(+)

diff --git a/gcc/config/rs6000/rs6000-cpus.def b/gcc/config/rs6000/rs6000-cpus.def
index b402079090f..c6e545ca71e 100644
--- a/gcc/config/rs6000/rs6000-cpus.def
+++ b/gcc/config/rs6000/rs6000-cpus.def
@@ -138,6 +138,7 @@
 				 | OPTION_MASK_FLOAT128_HW		\
 				 | OPTION_MASK_FLOAT128_KEYWORD		\
 				 | OPTION_MASK_FPRND			\
+				 | OPTION_MASK_LAGEN			\
 				 | OPTION_MASK_POWER10			\
 				 | OPTION_MASK_P10_FUSION		\
 				 | OPTION_MASK_HTM			\
diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index 378088b04c1..314a3641f85 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -6095,6 +6095,35 @@ rs6000_file_start (void)
 
   if (DEFAULT_ABI == ABI_ELFv2)
     fprintf (file, "\t.abiversion 2\n");
+
+  if (TARGET_LAGEN)
+    {
+      fprintf (file, "\n");
+      fprintf (file, "\t.macro lagen rt,ra,rb,n\n");
+      fprintf (file, "\tsldi \\rt,\\rb,\\n\n");
+      fprintf (file, "\tadd \\rt,\\rt,\\ra\n");
+      fprintf (file, "\t.endm\n");
+      fprintf (file, "\n");
+
+      fprintf (file, "\t.macro plagen1 rt,d,rb,n\n");
+      fprintf (file, "\tsldi \\rt,\\rb,\\n\n");
+      fprintf (file, "\tpaddi \\rt,\\rt,\\d\n");
+      fprintf (file, "\t.endm\n");
+      fprintf (file, "\n");
+
+      fprintf (file, "\t.macro plagen2 rt,d,ra,rb,n\n");
+      fprintf (file, "\tsldi \\rt,\\rb,\\n\n");
+      fprintf (file, "\tadd \\rt,\\rt,\\ra\n");
+      fprintf (file, "\tpaddi \\rt,\\rt,\\d\n");
+      fprintf (file, "\t.endm\n");
+      fprintf (file, "\n");
+
+      fprintf (file, "\t.macro plagen3 rt,d,ra,rb\n");
+      fprintf (file, "\tadd \\rt,\\rb,\\ra\n");
+      fprintf (file, "\tpaddi \\rt,\\rt,\\d\n");
+      fprintf (file, "\t.endm\n");
+      fprintf (file, "\n");
+    }
 }
 
 \f
@@ -24326,6 +24355,7 @@ static struct rs6000_opt_mask const rs6000_opt_masks[] =
   { "hard-dfp",			OPTION_MASK_DFP,		false, true  },
   { "htm",			OPTION_MASK_HTM,		false, true  },
   { "isel",			OPTION_MASK_ISEL,		false, true  },
+  { "lagen",			OPTION_MASK_LAGEN,		false, true  },
   { "mfcrf",			OPTION_MASK_MFCRF,		false, true  },
   { "mfpgpr",			0,				false, true  },
   { "mma",			OPTION_MASK_MMA,		false, true  },
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index fdf8ab9e2df..b84a04bd184 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -15581,6 +15581,48 @@
 }
   [(set_attr "type" "load")])
 \f
+;; RFC 2679, Scaled index address generation
+(define_insn "*lagendi3"
+  [(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
+	(plus:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
+			    (match_operand 2 "u5bit_cint_operand" "n"))
+		 (match_operand:DI 3 "base_reg_operand" "b")))]
+  "TARGET_LAGEN"
+  "lagen %0,%3,%1,%2"
+  [(set_attr "type" "shift")])
+
+(define_insn "*plagendi3_nora"
+  [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
+	(plus:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
+			    (match_operand 2 "u5bit_cint_operand" "n"))
+		 (match_operand 3 "s32bit_cint_operand" "n")))]
+  "TARGET_LAGEN && TARGET_PREFIXED"
+  "plagen1 %0,%3,%1,%2"			;; "plagen %0,%3(0),%1,%2"
+  [(set_attr "type" "shift")
+   (set_attr "prefixed" "yes")])
+
+(define_insn "*plagendi3"
+  [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
+	(plus:DI (plus:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r")
+				     (match_operand 2 "u5bit_cint_operand" "n"))
+			  (match_operand:DI 3 "base_reg_operand" "b"))
+		 (match_operand 4 "s32bit_cint_operand" "n")))]
+  "TARGET_LAGEN && TARGET_PREFIXED"
+  "plagen2 %0,%4,%3,%1,%2"		;; "plagen %0,%4(%3),%1,%2"
+  [(set_attr "type" "shift")
+   (set_attr "prefixed" "yes")])
+
+(define_insn "*plagendi3_noshift"
+  [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
+	(plus:DI (plus:DI (match_operand:DI 1 "base_reg_operand" "b")
+			  (match_operand:DI 2 "gpc_reg_operand" "r"))
+		 (match_operand 3 "s32bit_cint_operand" "n")))]
+  "TARGET_LAGEN && TARGET_PREFIXED"
+  "plagen3 %0,%3,%1,%2"			;; "plagen %0,%3(%1),%2,0"
+  [(set_attr "type" "shift")
+   (set_attr "prefixed" "yes")])
+
+\f
 
 (include "sync.md")
 (include "vector.md")
diff --git a/gcc/config/rs6000/rs6000.opt b/gcc/config/rs6000/rs6000.opt
index f3e8a0f1755..b1d27ab9eb0 100644
--- a/gcc/config/rs6000/rs6000.opt
+++ b/gcc/config/rs6000/rs6000.opt
@@ -624,6 +624,10 @@ mdmf
 Target Mask(DMF) Var(rs6000_isa_flags)
 Generate (do not generate) DMF instructions.
 
+mlagen
+Target Undocumented Mask(LAGEN) Var(rs6000_isa_flags)
+Generate (do not generate) LAGEN instructions.
+
 ; Documented parameters
 
 -param=rs6000-vect-unroll-limit=