From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 2153) id 028723856DC0; Fri, 21 Oct 2022 16:35:25 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 028723856DC0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1666370125; bh=x5IW36uQJLPyHzIdvc0VO+ehXFNSYOXwudRAIMKZEmY=; h=From:To:Subject:Date:From; b=Q2RTBSwL4mi4pINEM+LPpQpMW+qjHON587xWwyY7aMTJjtnIAB3go2febLQoN/8WC Zc0L28acT/9CEmhQoTQclEHsKx1cO2ZXRXgC/RemFC9yRryr1GwdrnA8In2j+SilBg thI3fSSRuRVhjODet0dc2e8L6MIfrmo+gH0mcj1I= MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="utf-8" From: Jakub Jelinek To: gcc-cvs@gcc.gnu.org Subject: [gcc r13-3439] i386: Fix up BFmode comparisons in conditional moves [PR107322] X-Act-Checkin: gcc X-Git-Author: Jakub Jelinek X-Git-Refname: refs/heads/master X-Git-Oldrev: 2cc41601d9a948e8d612a21c3b9a44ce0b977747 X-Git-Newrev: 5792208f5124f687376f25798668d105d7ddb270 Message-Id: <20221021163525.028723856DC0@sourceware.org> Date: Fri, 21 Oct 2022 16:35:25 +0000 (GMT) List-Id: https://gcc.gnu.org/g:5792208f5124f687376f25798668d105d7ddb270 commit r13-3439-g5792208f5124f687376f25798668d105d7ddb270 Author: Jakub Jelinek Date: Fri Oct 21 18:34:37 2022 +0200 i386: Fix up BFmode comparisons in conditional moves [PR107322] As the testcase shows, when cbranchbf4/cstorebf4 patterns are defined, we can get ICEs for conditional moves. The problem is that the generic conditional move expansion just calls prepare_cmp_insn which just checks that such a cbranch4 exists and returns directly such comparison and passes it down to the conditional move optabs. The following patch fixes it by punting if the comparisons aren't ix86_fp_comparison_operator (to tell the generic code it should separately compare) and to handle the promotion of BFmode comparison operands to SFmode such that comparison is performed in SFmode. 2022-10-21 Jakub Jelinek PR target/107322 * config/i386/i386-expand.cc (ix86_prepare_fp_compare_args): For BFmode comparisons promote arguments to SFmode and recurse. (ix86_expand_int_movcc, ix86_expand_fp_movcc): Return false early if comparison operands are BFmode and operands[1] is not ix86_fp_comparison_operator. * gcc.target/i386/pr107322.c: New test. Diff: --- gcc/config/i386/i386-expand.cc | 37 ++++++++++++++++++++++++++++++++ gcc/testsuite/gcc.target/i386/pr107322.c | 33 ++++++++++++++++++++++++++++ 2 files changed, 70 insertions(+) diff --git a/gcc/config/i386/i386-expand.cc b/gcc/config/i386/i386-expand.cc index 0e8ba144551..5d9e5a12f7e 100644 --- a/gcc/config/i386/i386-expand.cc +++ b/gcc/config/i386/i386-expand.cc @@ -2626,6 +2626,35 @@ ix86_prepare_fp_compare_args (enum rtx_code code, rtx *pop0, rtx *pop1) machine_mode op_mode = GET_MODE (op0); bool is_sse = SSE_FLOAT_MODE_SSEMATH_OR_HF_P (op_mode); + if (op_mode == BFmode) + { + rtx op = gen_lowpart (HImode, op0); + if (CONST_INT_P (op)) + op = simplify_const_unary_operation (FLOAT_EXTEND, SFmode, + op0, BFmode); + else + { + rtx t1 = gen_reg_rtx (SImode); + emit_insn (gen_zero_extendhisi2 (t1, op)); + emit_insn (gen_ashlsi3 (t1, t1, GEN_INT (16))); + op = gen_lowpart (SFmode, t1); + } + *pop0 = op; + op = gen_lowpart (HImode, op1); + if (CONST_INT_P (op)) + op = simplify_const_unary_operation (FLOAT_EXTEND, SFmode, + op1, BFmode); + else + { + rtx t1 = gen_reg_rtx (SImode); + emit_insn (gen_zero_extendhisi2 (t1, op)); + emit_insn (gen_ashlsi3 (t1, t1, GEN_INT (16))); + op = gen_lowpart (SFmode, t1); + } + *pop1 = op; + return ix86_prepare_fp_compare_args (code, pop0, pop1); + } + /* All of the unordered compare instructions only work on registers. The same is true of the fcomi compare instructions. The XFmode compare instructions require registers except when comparing @@ -3164,6 +3193,10 @@ ix86_expand_int_movcc (rtx operands[]) && !TARGET_64BIT)) return false; + if (GET_MODE (op0) == BFmode + && !ix86_fp_comparison_operator (operands[1], VOIDmode)) + return false; + start_sequence (); compare_op = ix86_expand_compare (code, op0, op1); compare_seq = get_insns (); @@ -4238,6 +4271,10 @@ ix86_expand_fp_movcc (rtx operands[]) rtx op0 = XEXP (operands[1], 0); rtx op1 = XEXP (operands[1], 1); + if (GET_MODE (op0) == BFmode + && !ix86_fp_comparison_operator (operands[1], VOIDmode)) + return false; + if (SSE_FLOAT_MODE_SSEMATH_OR_HF_P (mode)) { machine_mode cmode; diff --git a/gcc/testsuite/gcc.target/i386/pr107322.c b/gcc/testsuite/gcc.target/i386/pr107322.c new file mode 100644 index 00000000000..d3d11fe1662 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr107322.c @@ -0,0 +1,33 @@ +/* PR target/107322 */ +/* { dg-do compile } */ +/* { dg-options "-fexcess-precision=16 -O -msse2 -mfpmath=sse" } */ + +int i, j; +float k, l; +__bf16 f; + +void +foo (void) +{ + i *= 0 >= f; +} + +void +bar (void) +{ + i *= 0 <= f; +} + +void +baz (int x, int y) +{ + i = 0 >= f ? x : y; + j = 0 <= f ? x + 2 : y + 3; +} + +void +qux (float x, float y) +{ + k = 0 >= f ? x : y; + l = 0 <= f ? x + 2 : y + 3; +}