From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 2093) id D6823398C3C7; Wed, 26 Oct 2022 08:37:20 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org D6823398C3C7 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1666773440; bh=zWiyxzD685vglKACfINX41Boegt2cxeeDTnbUBURU6k=; h=From:To:Subject:Date:From; b=q/5AoUJn2n1bvKO2IfZegABeSosfxQLBwlzAb8PmSCudnjzZqOPKJkxRy2OQy/BaF Qr43air6L7coaiMtZk5FU3YoHtgUKly4mAB/sKDR5hEMbtV4nQ6KFaABq03v11tagD g4b7narpFRLa1UOp/PegxwuBwq/Tsd1xXemJF1Hg= MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="utf-8" From: Kito Cheng To: gcc-cvs@gcc.gnu.org Subject: [gcc r13-3502] RISC-V: Adjust table indentation in commnet for riscv-modes.def X-Act-Checkin: gcc X-Git-Author: Ju-Zhe Zhong X-Git-Refname: refs/heads/master X-Git-Oldrev: ba2030b078fdb2b5c6d77a696e635c175f5055df X-Git-Newrev: 0ef04aa86a4c7a7535ef1fac02c2457282bc9172 Message-Id: <20221026083720.D6823398C3C7@sourceware.org> Date: Wed, 26 Oct 2022 08:37:20 +0000 (GMT) List-Id: https://gcc.gnu.org/g:0ef04aa86a4c7a7535ef1fac02c2457282bc9172 commit r13-3502-g0ef04aa86a4c7a7535ef1fac02c2457282bc9172 Author: Ju-Zhe Zhong Date: Mon Oct 24 22:24:14 2022 +0800 RISC-V: Adjust table indentation in commnet for riscv-modes.def gcc/ChangeLog: * config/riscv/riscv-modes.def: Adjust table indentation in commnet. Diff: --- gcc/config/riscv/riscv-modes.def | 46 ++++++++++++++++++++-------------------- 1 file changed, 23 insertions(+), 23 deletions(-) diff --git a/gcc/config/riscv/riscv-modes.def b/gcc/config/riscv/riscv-modes.def index 95f69e87e23..ea88442e117 100644 --- a/gcc/config/riscv/riscv-modes.def +++ b/gcc/config/riscv/riscv-modes.def @@ -71,29 +71,29 @@ ADJUST_BYTESIZE (VNx64BI, riscv_vector_chunks * riscv_bytes_per_vector_chunk); /* | Mode | MIN_VLEN=32 | MIN_VLEN=32 | MIN_VLEN=64 | MIN_VLEN=64 | - | | LMUL | SEW/LMUL | LMUL | SEW/LMUL | - | VNx1QI | MF4 | 32 | MF8 | 64 | - | VNx2QI | MF2 | 16 | MF4 | 32 | - | VNx4QI | M1 | 8 | MF2 | 16 | - | VNx8QI | M2 | 4 | M1 | 8 | - | VNx16QI | M4 | 2 | M2 | 4 | - | VNx32QI | M8 | 1 | M4 | 2 | - | VNx64QI | N/A | N/A | M8 | 1 | - | VNx1(HI|HF) | MF2 | 32 | MF4 | 64 | - | VNx2(HI|HF) | M1 | 16 | MF2 | 32 | - | VNx4(HI|HF) | M2 | 8 | M1 | 16 | - | VNx8(HI|HF) | M4 | 4 | M2 | 8 | - | VNx16(HI|HF)| M8 | 2 | M4 | 4 | - | VNx32(HI|HF)| N/A | N/A | M8 | 2 | - | VNx1(SI|SF) | M1 | 32 | MF2 | 64 | - | VNx2(SI|SF) | M2 | 16 | M1 | 32 | - | VNx4(SI|SF) | M4 | 8 | M2 | 16 | - | VNx8(SI|SF) | M8 | 4 | M4 | 8 | - | VNx16(SI|SF)| N/A | N/A | M8 | 4 | - | VNx1(DI|DF) | N/A | N/A | M1 | 64 | - | VNx2(DI|DF) | N/A | N/A | M2 | 32 | - | VNx4(DI|DF) | N/A | N/A | M4 | 16 | - | VNx8(DI|DF) | N/A | N/A | M8 | 8 | + | | LMUL | SEW/LMUL | LMUL | SEW/LMUL | + | VNx1QI | MF4 | 32 | MF8 | 64 | + | VNx2QI | MF2 | 16 | MF4 | 32 | + | VNx4QI | M1 | 8 | MF2 | 16 | + | VNx8QI | M2 | 4 | M1 | 8 | + | VNx16QI | M4 | 2 | M2 | 4 | + | VNx32QI | M8 | 1 | M4 | 2 | + | VNx64QI | N/A | N/A | M8 | 1 | + | VNx1(HI|HF) | MF2 | 32 | MF4 | 64 | + | VNx2(HI|HF) | M1 | 16 | MF2 | 32 | + | VNx4(HI|HF) | M2 | 8 | M1 | 16 | + | VNx8(HI|HF) | M4 | 4 | M2 | 8 | + | VNx16(HI|HF)| M8 | 2 | M4 | 4 | + | VNx32(HI|HF)| N/A | N/A | M8 | 2 | + | VNx1(SI|SF) | M1 | 32 | MF2 | 64 | + | VNx2(SI|SF) | M2 | 16 | M1 | 32 | + | VNx4(SI|SF) | M4 | 8 | M2 | 16 | + | VNx8(SI|SF) | M8 | 4 | M4 | 8 | + | VNx16(SI|SF)| N/A | N/A | M8 | 4 | + | VNx1(DI|DF) | N/A | N/A | M1 | 64 | + | VNx2(DI|DF) | N/A | N/A | M2 | 32 | + | VNx4(DI|DF) | N/A | N/A | M4 | 16 | + | VNx8(DI|DF) | N/A | N/A | M8 | 8 | */ /* Define RVV modes whose sizes are multiples of 64-bit chunks. */