From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 2093) id F210D382EA35; Thu, 27 Oct 2022 03:17:57 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org F210D382EA35 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1666840685; bh=W34liv16m7FP43N8ZEXAYVDVRZNbHFXy7dCqxUnmZ1w=; h=From:To:Subject:Date:From; b=l0IvTtKeGXO1Y8LuRebds6xK+HTy7lD0Nc7yflqB1Sth+RHKu3YmYqUu0kf9k0hrM utlRDKfDm2ufs5+wPl7JIR3D0dkKr1vGyoLAj0JUupI9UGI//82YU14rs+a8LS1VjD ZC4RnBFrQBkWaJU1DCKL2aJCI8RY6y+hgZ4Yv31w= MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain; charset="utf-8" From: Kito Cheng To: gcc-cvs@gcc.gnu.org Subject: [gcc r13-3517] RISC-V: Minimal support of z*inx extension. X-Act-Checkin: gcc X-Git-Author: Jiawei X-Git-Refname: refs/heads/master X-Git-Oldrev: 486a50374e7c6200c476e67ffbe13ad71ac3262a X-Git-Newrev: e09335728d3f9bc177eac2f7dff79715e0aa67c9 Message-Id: <20221027031805.F210D382EA35@sourceware.org> Date: Thu, 27 Oct 2022 03:17:57 +0000 (GMT) List-Id: https://gcc.gnu.org/g:e09335728d3f9bc177eac2f7dff79715e0aa67c9 commit r13-3517-ge09335728d3f9bc177eac2f7dff79715e0aa67c9 Author: Jiawei Date: Thu Oct 20 17:32:32 2022 +0800 RISC-V: Minimal support of z*inx extension. Minimal support of z*inx extension, include 'zfinx'， 'zdinx' and 'zhinx/zhinxmin' corresponding to 'f', 'd' and 'zfh/zfhmin', the 'zdinx' will imply 'zfinx' same as 'd' imply 'f', 'zhinx' will aslo imply 'zfinx', all zfinx extension imply 'zicsr'. Co-Authored-By: Sinan Lin gcc/ChangeLog: * common/config/riscv/riscv-common.cc: New extensions. * config/riscv/arch-canonicalize: New imply relations. * config/riscv/riscv-opts.h (MASK_ZFINX): New mask. (MASK_ZDINX): Ditto. (MASK_ZHINX): Ditto. (MASK_ZHINXMIN): Ditto. (TARGET_ZFINX): New target. (TARGET_ZDINX): Ditto. (TARGET_ZHINX): Ditto. (TARGET_ZHINXMIN): Ditto. * config/riscv/riscv.opt: New target variable. Diff: --- gcc/common/config/riscv/riscv-common.cc | 18 ++++++++++++++++++ gcc/config/riscv/arch-canonicalize | 5 +++++ gcc/config/riscv/riscv-opts.h | 10 ++++++++++ gcc/config/riscv/riscv.opt | 3 +++ 4 files changed, 36 insertions(+) diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc index bd356ce2093..d6404a01205 100644 --- a/gcc/common/config/riscv/riscv-common.cc +++ b/gcc/common/config/riscv/riscv-common.cc @@ -51,6 +51,11 @@ static const riscv_implied_info_t riscv_implied_info[] = {"d", "f"}, {"f", "zicsr"}, {"d", "zicsr"}, + + {"zdinx", "zfinx"}, + {"zfinx", "zicsr"}, + {"zdinx", "zicsr"}, + {"zk", "zkn"}, {"zk", "zkr"}, {"zk", "zkt"}, @@ -99,6 +104,9 @@ static const riscv_implied_info_t riscv_implied_info[] = {"zfh", "zfhmin"}, {"zfhmin", "f"}, + + {"zhinx", "zhinxmin"}, + {"zhinxmin", "zfinx"}, {NULL, NULL} }; @@ -160,6 +168,11 @@ static const struct riscv_ext_version riscv_ext_version_table[] = {"zbc", ISA_SPEC_CLASS_NONE, 1, 0}, {"zbs", ISA_SPEC_CLASS_NONE, 1, 0}, + {"zfinx", ISA_SPEC_CLASS_NONE, 1, 0}, + {"zdinx", ISA_SPEC_CLASS_NONE, 1, 0}, + {"zhinx", ISA_SPEC_CLASS_NONE, 1, 0}, + {"zhinxmin", ISA_SPEC_CLASS_NONE, 1, 0}, + {"zbkb", ISA_SPEC_CLASS_NONE, 1, 0}, {"zbkc", ISA_SPEC_CLASS_NONE, 1, 0}, {"zbkx", ISA_SPEC_CLASS_NONE, 1, 0}, @@ -1172,6 +1185,11 @@ static const riscv_ext_flag_table_t riscv_ext_flag_table[] = {"zbc", &gcc_options::x_riscv_zb_subext, MASK_ZBC}, {"zbs", &gcc_options::x_riscv_zb_subext, MASK_ZBS}, + {"zfinx", &gcc_options::x_riscv_zinx_subext, MASK_ZFINX}, + {"zdinx", &gcc_options::x_riscv_zinx_subext, MASK_ZDINX}, + {"zhinx", &gcc_options::x_riscv_zinx_subext, MASK_ZHINX}, + {"zhinxmin", &gcc_options::x_riscv_zinx_subext, MASK_ZHINXMIN}, + {"zbkb", &gcc_options::x_riscv_zk_subext, MASK_ZBKB}, {"zbkc", &gcc_options::x_riscv_zk_subext, MASK_ZBKC}, {"zbkx", &gcc_options::x_riscv_zk_subext, MASK_ZBKX}, diff --git a/gcc/config/riscv/arch-canonicalize b/gcc/config/riscv/arch-canonicalize index fd7651ac491..2498db506b7 100755 --- a/gcc/config/riscv/arch-canonicalize +++ b/gcc/config/riscv/arch-canonicalize @@ -41,6 +41,11 @@ LONG_EXT_PREFIXES = ['z', 's', 'h', 'x'] IMPLIED_EXT = { "d" : ["f", "zicsr"], "f" : ["zicsr"], + "zdinx" : ["zfinx", "zicsr"], + "zfinx" : ["zicsr"], + "zhinx" : ["zhinxmin", "zfinx", "zicsr"], + "zhinxmin" : ["zfinx", "zicsr"], + "zk" : ["zkn", "zkr", "zkt"], "zkn" : ["zbkb", "zbkc", "zbkx", "zkne", "zknd", "zknh"], "zks" : ["zbkb", "zbkc", "zbkx", "zksed", "zksh"], diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h index 63ac56a8ca0..1dfe8c89209 100644 --- a/gcc/config/riscv/riscv-opts.h +++ b/gcc/config/riscv/riscv-opts.h @@ -83,6 +83,16 @@ enum stack_protector_guard { #define TARGET_ZBC ((riscv_zb_subext & MASK_ZBC) != 0) #define TARGET_ZBS ((riscv_zb_subext & MASK_ZBS) != 0) +#define MASK_ZFINX (1 << 0) +#define MASK_ZDINX (1 << 1) +#define MASK_ZHINX (1 << 2) +#define MASK_ZHINXMIN (1 << 3) + +#define TARGET_ZFINX ((riscv_zinx_subext & MASK_ZFINX) != 0) +#define TARGET_ZDINX ((riscv_zinx_subext & MASK_ZDINX) != 0) +#define TARGET_ZHINX ((riscv_zinx_subext & MASK_ZHINX) != 0) +#define TARGET_ZHINXMIN ((riscv_zinx_subext & MASK_ZHINXMIN) != 0) + #define MASK_ZBKB (1 << 0) #define MASK_ZBKC (1 << 1) #define MASK_ZBKX (1 << 2) diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt index 949311775c1..426ea95cd14 100644 --- a/gcc/config/riscv/riscv.opt +++ b/gcc/config/riscv/riscv.opt @@ -206,6 +206,9 @@ int riscv_zi_subext TargetVariable int riscv_zb_subext +TargetVariable +int riscv_zinx_subext + TargetVariable int riscv_zk_subext