From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 2093) id 09AF13886C5C; Thu, 27 Oct 2022 03:18:02 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 09AF13886C5C DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1666840686; bh=MmwUJVeOrPIVyfFlq1lJi3XB/q4xwOem4C9y/05TEEM=; h=From:To:Subject:Date:From; b=SNWPMuKh1Z6XO1YWm2jpNwsM4ytoyXI4OUcB6yIqsC/34LFIpwmD5MC6cmUgHNvQn aRzek6HWcdc2ldZHGeqrXeiGsCAwbMG7bC6/ACUTJ7rJXeSvBOiEup4wVCncwa1k6P l7QqH2EwFZ2meCJm+q6KXRCQScdypNVyXXye/6n8= MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="utf-8" From: Kito Cheng To: gcc-cvs@gcc.gnu.org Subject: [gcc r13-3518] RISC-V: Target support for z*inx extension. X-Act-Checkin: gcc X-Git-Author: Jiawei X-Git-Refname: refs/heads/master X-Git-Oldrev: e09335728d3f9bc177eac2f7dff79715e0aa67c9 X-Git-Newrev: ac96e9068ce7dcaca992fde7f1551ffe8837b723 Message-Id: <20221027031806.09AF13886C5C@sourceware.org> Date: Thu, 27 Oct 2022 03:18:02 +0000 (GMT) List-Id: https://gcc.gnu.org/g:ac96e9068ce7dcaca992fde7f1551ffe8837b723 commit r13-3518-gac96e9068ce7dcaca992fde7f1551ffe8837b723 Author: Jiawei Date: Thu Oct 20 17:32:33 2022 +0800 RISC-V: Target support for z*inx extension. Support 'TARGET_ZFINX' with float instruction pattern and builtin function. Reuse 'TARGET_HADR_FLOAT', 'TARGET_DOUBLE_FLOAT' and 'TARGET_ZHINX' patterns. gcc/ChangeLog: * config/riscv/iterators.md (TARGET_ZFINX):New target. (TARGET_ZDINX): Ditto. (TARGET_ZHINX): Ditto. * config/riscv/riscv-builtins.cc (AVAIL): Ditto. (riscv_atomic_assign_expand_fenv): Ditto. * config/riscv/riscv-c.cc (riscv_cpu_cpp_builtins): Ditto. * config/riscv/riscv.md: Ditto. Diff: --- gcc/config/riscv/iterators.md | 6 +-- gcc/config/riscv/riscv-builtins.cc | 4 +- gcc/config/riscv/riscv-c.cc | 2 +- gcc/config/riscv/riscv.md | 78 +++++++++++++++++++------------------- 4 files changed, 46 insertions(+), 44 deletions(-) diff --git a/gcc/config/riscv/iterators.md b/gcc/config/riscv/iterators.md index 39dffabc235..50380ecfac9 100644 --- a/gcc/config/riscv/iterators.md +++ b/gcc/config/riscv/iterators.md @@ -59,9 +59,9 @@ (define_mode_iterator ANYI [QI HI SI (DI "TARGET_64BIT")]) ;; Iterator for hardware-supported floating-point modes. -(define_mode_iterator ANYF [(SF "TARGET_HARD_FLOAT") - (DF "TARGET_DOUBLE_FLOAT") - (HF "TARGET_ZFH")]) +(define_mode_iterator ANYF [(SF "TARGET_HARD_FLOAT || TARGET_ZFINX") + (DF "TARGET_DOUBLE_FLOAT || TARGET_ZDINX") + (HF "TARGET_ZFH || TARGET_ZHINX")]) ;; Iterator for floating-point modes that can be loaded into X registers. (define_mode_iterator SOFTF [SF (DF "TARGET_64BIT") (HF "TARGET_ZFHMIN")]) diff --git a/gcc/config/riscv/riscv-builtins.cc b/gcc/config/riscv/riscv-builtins.cc index 9fa4d6cffd8..021f6c6b69a 100644 --- a/gcc/config/riscv/riscv-builtins.cc +++ b/gcc/config/riscv/riscv-builtins.cc @@ -87,7 +87,7 @@ struct riscv_builtin_description { unsigned int (*avail) (void); }; -AVAIL (hard_float, TARGET_HARD_FLOAT) +AVAIL (hard_float, TARGET_HARD_FLOAT || TARGET_ZFINX) AVAIL (clean32, TARGET_ZICBOM && !TARGET_64BIT) @@ -342,7 +342,7 @@ riscv_expand_builtin (tree exp, rtx target, rtx subtarget ATTRIBUTE_UNUSED, void riscv_atomic_assign_expand_fenv (tree *hold, tree *clear, tree *update) { - if (!TARGET_HARD_FLOAT) + if (!(TARGET_HARD_FLOAT || TARGET_ZFINX)) return; tree frflags = GET_BUILTIN_DECL (CODE_FOR_riscv_frflags); diff --git a/gcc/config/riscv/riscv-c.cc b/gcc/config/riscv/riscv-c.cc index 78f6eacb068..826ae0067bb 100644 --- a/gcc/config/riscv/riscv-c.cc +++ b/gcc/config/riscv/riscv-c.cc @@ -61,7 +61,7 @@ riscv_cpu_cpp_builtins (cpp_reader *pfile) if (TARGET_HARD_FLOAT) builtin_define_with_int_value ("__riscv_flen", UNITS_PER_FP_REG * 8); - if (TARGET_HARD_FLOAT && TARGET_FDIV) + if ((TARGET_HARD_FLOAT || TARGET_ZFINX) && TARGET_FDIV) { builtin_define ("__riscv_fdiv"); builtin_define ("__riscv_fsqrt"); diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md index ae907a75126..798f7370a08 100644 --- a/gcc/config/riscv/riscv.md +++ b/gcc/config/riscv/riscv.md @@ -441,7 +441,7 @@ [(set (match_operand:ANYF 0 "register_operand" "=f") (plus:ANYF (match_operand:ANYF 1 "register_operand" " f") (match_operand:ANYF 2 "register_operand" " f")))] - "TARGET_HARD_FLOAT" + "TARGET_HARD_FLOAT || TARGET_ZFINX" "fadd.\t%0,%1,%2" [(set_attr "type" "fadd") (set_attr "mode" "")]) @@ -572,7 +572,7 @@ [(set (match_operand:ANYF 0 "register_operand" "=f") (minus:ANYF (match_operand:ANYF 1 "register_operand" " f") (match_operand:ANYF 2 "register_operand" " f")))] - "TARGET_HARD_FLOAT" + "TARGET_HARD_FLOAT || TARGET_ZFINX" "fsub.\t%0,%1,%2" [(set_attr "type" "fadd") (set_attr "mode" "")]) @@ -742,7 +742,7 @@ [(set (match_operand:ANYF 0 "register_operand" "=f") (mult:ANYF (match_operand:ANYF 1 "register_operand" " f") (match_operand:ANYF 2 "register_operand" " f")))] - "TARGET_HARD_FLOAT" + "TARGET_HARD_FLOAT || TARGET_ZFINX" "fmul.\t%0,%1,%2" [(set_attr "type" "fmul") (set_attr "mode" "")]) @@ -1049,7 +1049,7 @@ [(set (match_operand:ANYF 0 "register_operand" "=f") (div:ANYF (match_operand:ANYF 1 "register_operand" " f") (match_operand:ANYF 2 "register_operand" " f")))] - "TARGET_HARD_FLOAT && TARGET_FDIV" + "(TARGET_HARD_FLOAT || TARGET_ZFINX) && TARGET_FDIV" "fdiv.\t%0,%1,%2" [(set_attr "type" "fdiv") (set_attr "mode" "")]) @@ -1064,7 +1064,7 @@ (define_insn "sqrt2" [(set (match_operand:ANYF 0 "register_operand" "=f") (sqrt:ANYF (match_operand:ANYF 1 "register_operand" " f")))] - "TARGET_HARD_FLOAT && TARGET_FDIV" + "(TARGET_HARD_FLOAT || TARGET_ZFINX) && TARGET_FDIV" { return "fsqrt.\t%0,%1"; } @@ -1079,7 +1079,7 @@ (fma:ANYF (match_operand:ANYF 1 "register_operand" " f") (match_operand:ANYF 2 "register_operand" " f") (match_operand:ANYF 3 "register_operand" " f")))] - "TARGET_HARD_FLOAT" + "TARGET_HARD_FLOAT || TARGET_ZFINX" "fmadd.\t%0,%1,%2,%3" [(set_attr "type" "fmadd") (set_attr "mode" "")]) @@ -1090,7 +1090,7 @@ (fma:ANYF (match_operand:ANYF 1 "register_operand" " f") (match_operand:ANYF 2 "register_operand" " f") (neg:ANYF (match_operand:ANYF 3 "register_operand" " f"))))] - "TARGET_HARD_FLOAT" + "TARGET_HARD_FLOAT || TARGET_ZFINX" "fmsub.\t%0,%1,%2,%3" [(set_attr "type" "fmadd") (set_attr "mode" "")]) @@ -1102,7 +1102,7 @@ (neg:ANYF (match_operand:ANYF 1 "register_operand" " f")) (match_operand:ANYF 2 "register_operand" " f") (neg:ANYF (match_operand:ANYF 3 "register_operand" " f"))))] - "TARGET_HARD_FLOAT" + "TARGET_HARD_FLOAT || TARGET_ZFINX" "fnmadd.\t%0,%1,%2,%3" [(set_attr "type" "fmadd") (set_attr "mode" "")]) @@ -1114,7 +1114,7 @@ (neg:ANYF (match_operand:ANYF 1 "register_operand" " f")) (match_operand:ANYF 2 "register_operand" " f") (match_operand:ANYF 3 "register_operand" " f")))] - "TARGET_HARD_FLOAT" + "TARGET_HARD_FLOAT || TARGET_ZFINX" "fnmsub.\t%0,%1,%2,%3" [(set_attr "type" "fmadd") (set_attr "mode" "")]) @@ -1127,7 +1127,7 @@ (neg:ANYF (match_operand:ANYF 1 "register_operand" " f")) (match_operand:ANYF 2 "register_operand" " f") (neg:ANYF (match_operand:ANYF 3 "register_operand" " f")))))] - "TARGET_HARD_FLOAT && !HONOR_SIGNED_ZEROS (mode)" + "(TARGET_HARD_FLOAT || TARGET_ZFINX) && !HONOR_SIGNED_ZEROS (mode)" "fmadd.\t%0,%1,%2,%3" [(set_attr "type" "fmadd") (set_attr "mode" "")]) @@ -1140,7 +1140,7 @@ (neg:ANYF (match_operand:ANYF 1 "register_operand" " f")) (match_operand:ANYF 2 "register_operand" " f") (match_operand:ANYF 3 "register_operand" " f"))))] - "TARGET_HARD_FLOAT && !HONOR_SIGNED_ZEROS (mode)" + "(TARGET_HARD_FLOAT || TARGET_ZFINX) && !HONOR_SIGNED_ZEROS (mode)" "fmsub.\t%0,%1,%2,%3" [(set_attr "type" "fmadd") (set_attr "mode" "")]) @@ -1153,7 +1153,7 @@ (match_operand:ANYF 1 "register_operand" " f") (match_operand:ANYF 2 "register_operand" " f") (match_operand:ANYF 3 "register_operand" " f"))))] - "TARGET_HARD_FLOAT && !HONOR_SIGNED_ZEROS (mode)" + "(TARGET_HARD_FLOAT || TARGET_ZFINX) && !HONOR_SIGNED_ZEROS (mode)" "fnmadd.\t%0,%1,%2,%3" [(set_attr "type" "fmadd") (set_attr "mode" "")]) @@ -1166,7 +1166,7 @@ (match_operand:ANYF 1 "register_operand" " f") (match_operand:ANYF 2 "register_operand" " f") (neg:ANYF (match_operand:ANYF 3 "register_operand" " f")))))] - "TARGET_HARD_FLOAT && !HONOR_SIGNED_ZEROS (mode)" + "(TARGET_HARD_FLOAT || TARGET_ZFINX) && !HONOR_SIGNED_ZEROS (mode)" "fnmsub.\t%0,%1,%2,%3" [(set_attr "type" "fmadd") (set_attr "mode" "")]) @@ -1181,7 +1181,7 @@ (define_insn "abs2" [(set (match_operand:ANYF 0 "register_operand" "=f") (abs:ANYF (match_operand:ANYF 1 "register_operand" " f")))] - "TARGET_HARD_FLOAT" + "TARGET_HARD_FLOAT || TARGET_ZFINX" "fabs.\t%0,%1" [(set_attr "type" "fmove") (set_attr "mode" "")]) @@ -1191,7 +1191,7 @@ (unspec:ANYF [(match_operand:ANYF 1 "register_operand" " f") (match_operand:ANYF 2 "register_operand" " f")] UNSPEC_COPYSIGN))] - "TARGET_HARD_FLOAT" + "TARGET_HARD_FLOAT || TARGET_ZFINX" "fsgnj.\t%0,%1,%2" [(set_attr "type" "fmove") (set_attr "mode" "")]) @@ -1199,7 +1199,7 @@ (define_insn "neg2" [(set (match_operand:ANYF 0 "register_operand" "=f") (neg:ANYF (match_operand:ANYF 1 "register_operand" " f")))] - "TARGET_HARD_FLOAT" + "TARGET_HARD_FLOAT || TARGET_ZFINX" "fneg.\t%0,%1" [(set_attr "type" "fmove") (set_attr "mode" "")]) @@ -1216,7 +1216,7 @@ (unspec:ANYF [(use (match_operand:ANYF 1 "register_operand" " f")) (use (match_operand:ANYF 2 "register_operand" " f"))] UNSPEC_FMIN))] - "TARGET_HARD_FLOAT && !HONOR_SNANS (mode)" + "(TARGET_HARD_FLOAT || TARGET_ZFINX) && !HONOR_SNANS (mode)" "fmin.\t%0,%1,%2" [(set_attr "type" "fmove") (set_attr "mode" "")]) @@ -1226,7 +1226,7 @@ (unspec:ANYF [(use (match_operand:ANYF 1 "register_operand" " f")) (use (match_operand:ANYF 2 "register_operand" " f"))] UNSPEC_FMAX))] - "TARGET_HARD_FLOAT && !HONOR_SNANS (mode)" + "(TARGET_HARD_FLOAT || TARGET_ZFINX) && !HONOR_SNANS (mode)" "fmax.\t%0,%1,%2" [(set_attr "type" "fmove") (set_attr "mode" "")]) @@ -1235,7 +1235,7 @@ [(set (match_operand:ANYF 0 "register_operand" "=f") (smin:ANYF (match_operand:ANYF 1 "register_operand" " f") (match_operand:ANYF 2 "register_operand" " f")))] - "TARGET_HARD_FLOAT" + "TARGET_HARD_FLOAT || TARGET_ZFINX" "fmin.\t%0,%1,%2" [(set_attr "type" "fmove") (set_attr "mode" "")]) @@ -1244,7 +1244,7 @@ [(set (match_operand:ANYF 0 "register_operand" "=f") (smax:ANYF (match_operand:ANYF 1 "register_operand" " f") (match_operand:ANYF 2 "register_operand" " f")))] - "TARGET_HARD_FLOAT" + "TARGET_HARD_FLOAT || TARGET_ZFINX" "fmax.\t%0,%1,%2" [(set_attr "type" "fmove") (set_attr "mode" "")]) @@ -1305,7 +1305,7 @@ [(set (match_operand:SF 0 "register_operand" "=f") (float_truncate:SF (match_operand:DF 1 "register_operand" " f")))] - "TARGET_DOUBLE_FLOAT" + "TARGET_DOUBLE_FLOAT || TARGET_ZDINX" "fcvt.s.d\t%0,%1" [(set_attr "type" "fcvt") (set_attr "mode" "SF")]) @@ -1314,7 +1314,7 @@ [(set (match_operand:HF 0 "register_operand" "=f") (float_truncate:HF (match_operand:SF 1 "register_operand" " f")))] - "TARGET_ZFHMIN" + "TARGET_ZFHMIN || TARGET_ZHINXMIN" "fcvt.h.s\t%0,%1" [(set_attr "type" "fcvt") (set_attr "mode" "HF")]) @@ -1323,7 +1323,8 @@ [(set (match_operand:HF 0 "register_operand" "=f") (float_truncate:HF (match_operand:DF 1 "register_operand" " f")))] - "TARGET_ZFHMIN && TARGET_DOUBLE_FLOAT" + "(TARGET_ZFHMIN && TARGET_DOUBLE_FLOAT) || + (TARGET_ZHINXMIN && TARGET_ZDINX)" "fcvt.h.d\t%0,%1" [(set_attr "type" "fcvt") (set_attr "mode" "HF")]) @@ -1449,7 +1450,7 @@ [(set (match_operand:SF 0 "register_operand" "=f") (float_extend:SF (match_operand:HF 1 "register_operand" " f")))] - "TARGET_ZFHMIN" + "TARGET_ZFHMIN || TARGET_ZHINXMIN" "fcvt.s.h\t%0,%1" [(set_attr "type" "fcvt") (set_attr "mode" "SF")]) @@ -1458,7 +1459,7 @@ [(set (match_operand:DF 0 "register_operand" "=f") (float_extend:DF (match_operand:SF 1 "register_operand" " f")))] - "TARGET_DOUBLE_FLOAT" + "TARGET_DOUBLE_FLOAT || TARGET_ZDINX" "fcvt.d.s\t%0,%1" [(set_attr "type" "fcvt") (set_attr "mode" "DF")]) @@ -1467,7 +1468,8 @@ [(set (match_operand:DF 0 "register_operand" "=f") (float_extend:DF (match_operand:HF 1 "register_operand" " f")))] - "TARGET_ZFHMIN && TARGET_DOUBLE_FLOAT" + "(TARGET_ZFHMIN && TARGET_DOUBLE_FLOAT) || + (TARGET_ZHINXMIN && TARGET_ZDINX)" "fcvt.d.h\t%0,%1" [(set_attr "type" "fcvt") (set_attr "mode" "DF")]) @@ -1513,7 +1515,7 @@ [(set (match_operand:GPR 0 "register_operand" "=r") (fix:GPR (match_operand:ANYF 1 "register_operand" " f")))] - "TARGET_HARD_FLOAT" + "TARGET_HARD_FLOAT || TARGET_ZFINX" "fcvt.. %0,%1,rtz" [(set_attr "type" "fcvt") (set_attr "mode" "")]) @@ -1522,7 +1524,7 @@ [(set (match_operand:GPR 0 "register_operand" "=r") (unsigned_fix:GPR (match_operand:ANYF 1 "register_operand" " f")))] - "TARGET_HARD_FLOAT" + "TARGET_HARD_FLOAT || TARGET_ZFINX" "fcvt.u. %0,%1,rtz" [(set_attr "type" "fcvt") (set_attr "mode" "")]) @@ -1531,7 +1533,7 @@ [(set (match_operand:ANYF 0 "register_operand" "= f") (float:ANYF (match_operand:GPR 1 "reg_or_0_operand" " rJ")))] - "TARGET_HARD_FLOAT" + "TARGET_HARD_FLOAT || TARGET_ZFINX" "fcvt..\t%0,%z1" [(set_attr "type" "fcvt") (set_attr "mode" "")]) @@ -1540,7 +1542,7 @@ [(set (match_operand:ANYF 0 "register_operand" "= f") (unsigned_float:ANYF (match_operand:GPR 1 "reg_or_0_operand" " rJ")))] - "TARGET_HARD_FLOAT" + "TARGET_HARD_FLOAT || TARGET_ZFINX" "fcvt..u\t%0,%z1" [(set_attr "type" "fcvt") (set_attr "mode" "")]) @@ -1550,7 +1552,7 @@ (unspec:GPR [(match_operand:ANYF 1 "register_operand" " f")] RINT))] - "TARGET_HARD_FLOAT" + "TARGET_HARD_FLOAT || TARGET_ZFINX" "fcvt.. %0,%1," [(set_attr "type" "fcvt") (set_attr "mode" "")]) @@ -2278,7 +2280,7 @@ (match_operand:ANYF 2 "register_operand")]) (label_ref (match_operand 3 "")) (pc)))] - "TARGET_HARD_FLOAT" + "TARGET_HARD_FLOAT || TARGET_ZFINX" { riscv_expand_conditional_branch (operands[3], GET_CODE (operands[0]), operands[1], operands[2]); @@ -2367,7 +2369,7 @@ (match_operator:SI 1 "fp_scc_comparison" [(match_operand:ANYF 2 "register_operand") (match_operand:ANYF 3 "register_operand")]))] - "TARGET_HARD_FLOAT" + "TARGET_HARD_FLOAT || TARGET_ZFINX" { riscv_expand_float_scc (operands[0], GET_CODE (operands[1]), operands[2], operands[3]); @@ -2379,7 +2381,7 @@ (match_operator:X 1 "fp_native_comparison" [(match_operand:ANYF 2 "register_operand" " f") (match_operand:ANYF 3 "register_operand" " f")]))] - "TARGET_HARD_FLOAT" + "TARGET_HARD_FLOAT || TARGET_ZFINX" "f%C1.\t%0,%2,%3" [(set_attr "type" "fcmp") (set_attr "mode" "")]) @@ -2389,7 +2391,7 @@ (unspec:X [(match_operand:ANYF 1 "register_operand") (match_operand:ANYF 2 "register_operand")] QUIET_COMPARISON))] - "TARGET_HARD_FLOAT" + "TARGET_HARD_FLOAT || TARGET_ZFINX" { rtx op0 = operands[0]; rtx op1 = operands[1]; @@ -2809,19 +2811,19 @@ (define_insn "riscv_frflags" [(set (match_operand:SI 0 "register_operand" "=r") (unspec_volatile [(const_int 0)] UNSPECV_FRFLAGS))] - "TARGET_HARD_FLOAT" + "TARGET_HARD_FLOAT || TARGET_ZFINX" "frflags\t%0") (define_insn "riscv_fsflags" [(unspec_volatile [(match_operand:SI 0 "csr_operand" "rK")] UNSPECV_FSFLAGS)] - "TARGET_HARD_FLOAT" + "TARGET_HARD_FLOAT || TARGET_ZFINX" "fsflags\t%0") (define_insn "*riscv_fsnvsnan2" [(unspec_volatile [(match_operand:ANYF 0 "register_operand" "f") (match_operand:ANYF 1 "register_operand" "f")] UNSPECV_FSNVSNAN)] - "TARGET_HARD_FLOAT" + "TARGET_HARD_FLOAT || TARGET_ZFINX" "feq.\tzero,%0,%1" [(set_attr "type" "fcmp") (set_attr "mode" "")])