From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 2093) id CB780382A2E0; Thu, 27 Oct 2022 03:18:07 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org CB780382A2E0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1666840687; bh=HBLeuVGRTupzplThFkkcb0qudvIeQx5asV1K7BO77iI=; h=From:To:Subject:Date:From; b=X6KWkjHmVhU7KKq7MipFAftx2vhauB22uNPowi9+e/O9Ip1dCYbuIMjL8rG7khSGg WxkEvNnfUDJuSgrQKHzutTWeUvPgGn7u5ByDI9UrOcTbPia6m2/hSdNmLfOI9bSw3p lV4f1lKCBydZDMG+rFHWOFZc2gkCBeAC0PGjC+wI= MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="utf-8" From: Kito Cheng To: gcc-cvs@gcc.gnu.org Subject: [gcc r13-3519] RISC-V: Limit regs use for z*inx extension. X-Act-Checkin: gcc X-Git-Author: Jiawei X-Git-Refname: refs/heads/master X-Git-Oldrev: ac96e9068ce7dcaca992fde7f1551ffe8837b723 X-Git-Newrev: 6b252dc96b52f5ab6f399c3f6b0c0b6614a36913 Message-Id: <20221027031807.CB780382A2E0@sourceware.org> Date: Thu, 27 Oct 2022 03:18:07 +0000 (GMT) List-Id: https://gcc.gnu.org/g:6b252dc96b52f5ab6f399c3f6b0c0b6614a36913 commit r13-3519-g6b252dc96b52f5ab6f399c3f6b0c0b6614a36913 Author: Jiawei Date: Thu Oct 20 17:32:34 2022 +0800 RISC-V: Limit regs use for z*inx extension. Limit z*inx abi support with 'ilp32','ilp32e','lp64' only. Use GPR instead FPR when 'zfinx' enable, Only use even registers in RV32 when 'zdinx' enable. Enable FLOAT16 when Zhinx/Zhinxmin enabled. Co-Authored-By: Sinan Lin gcc/ChangeLog: * config/riscv/constraints.md (TARGET_ZFINX ? GR_REGS): Set GPRS use while Zfinx is enable. * config/riscv/riscv.cc (riscv_hard_regno_mode_ok): Limit odd registers use when Zdinx enable in RV32 cases. (riscv_option_override): New target enable MASK_FDIV. (riscv_libgcc_floating_mode_supported_p): New error info when use incompatible arch&abi. (riscv_excess_precision): New target enable FLOAT16. Diff: --- gcc/config/riscv/constraints.md | 5 +++-- gcc/config/riscv/riscv.cc | 21 +++++++++++++++++---- 2 files changed, 20 insertions(+), 6 deletions(-) diff --git a/gcc/config/riscv/constraints.md b/gcc/config/riscv/constraints.md index 951dcc52d6b..4088c48150a 100644 --- a/gcc/config/riscv/constraints.md +++ b/gcc/config/riscv/constraints.md @@ -21,8 +21,9 @@ ;; Register constraints -(define_register_constraint "f" "TARGET_HARD_FLOAT ? FP_REGS : NO_REGS" - "A floating-point register (if available).") +(define_register_constraint "f" "TARGET_HARD_FLOAT ? FP_REGS : + (TARGET_ZFINX ? GR_REGS : NO_REGS)" + "A floating-point register (if available, reuse GPR as FPR when use zfinx).") (define_register_constraint "j" "SIBCALL_REGS" "@internal") diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index 3d02954ffce..77bc65b0881 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -5420,6 +5420,13 @@ riscv_hard_regno_mode_ok (unsigned int regno, machine_mode mode) != call_used_or_fixed_reg_p (regno + i)) return false; + /* Only use even registers in RV32 ZDINX */ + if (!TARGET_64BIT && TARGET_ZDINX){ + if (GET_MODE_CLASS (mode) == MODE_FLOAT && + GET_MODE_UNIT_SIZE (mode) == GET_MODE_SIZE (DFmode)) + return !(regno & 1); + } + return true; } @@ -5659,7 +5666,7 @@ riscv_option_override (void) error ("%<-mdiv%> requires %<-march%> to subsume the % extension"); /* Likewise floating-point division and square root. */ - if (TARGET_HARD_FLOAT && (target_flags_explicit & MASK_FDIV) == 0) + if ((TARGET_HARD_FLOAT || TARGET_ZFINX) && (target_flags_explicit & MASK_FDIV) == 0) target_flags |= MASK_FDIV; /* Handle -mtune, use -mcpu if -mtune is not given, and use default -mtune @@ -5705,6 +5712,11 @@ riscv_option_override (void) if (TARGET_RVE && riscv_abi != ABI_ILP32E) error ("rv32e requires ilp32e ABI"); + // Zfinx require abi ilp32,ilp32e or lp64. + if (TARGET_ZFINX && riscv_abi != ABI_ILP32 + && riscv_abi != ABI_LP64 && riscv_abi != ABI_ILP32E) + error ("z*inx requires ABI ilp32, ilp32e or lp64"); + /* We do not yet support ILP32 on RV64. */ if (BITS_PER_WORD != POINTER_SIZE) error ("ABI requires %<-march=rv%d%>", POINTER_SIZE); @@ -6337,7 +6349,7 @@ riscv_libgcc_floating_mode_supported_p (scalar_float_mode mode) precision of the _FloatN type; evaluate all other operations and constants to the range and precision of the semantic type; - If we have the zfh extensions then we support _Float16 in native + If we have the zfh/zhinx extensions then we support _Float16 in native precision, so we should set this to 16. */ static enum flt_eval_method riscv_excess_precision (enum excess_precision_type type) @@ -6346,8 +6358,9 @@ riscv_excess_precision (enum excess_precision_type type) { case EXCESS_PRECISION_TYPE_FAST: case EXCESS_PRECISION_TYPE_STANDARD: - return (TARGET_ZFH ? FLT_EVAL_METHOD_PROMOTE_TO_FLOAT16 - : FLT_EVAL_METHOD_PROMOTE_TO_FLOAT); + return ((TARGET_ZFH || TARGET_ZHINX) + ? FLT_EVAL_METHOD_PROMOTE_TO_FLOAT16 + : FLT_EVAL_METHOD_PROMOTE_TO_FLOAT); case EXCESS_PRECISION_TYPE_IMPLICIT: case EXCESS_PRECISION_TYPE_FLOAT16: return FLT_EVAL_METHOD_PROMOTE_TO_FLOAT16;