From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1005) id 75863382A2FF; Thu, 27 Oct 2022 03:36:15 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 75863382A2FF DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1666841775; bh=FtDptsRkO96yvgZ+5RUpC7v1gh2ZL3ln41YvAxsuUss=; h=From:To:Subject:Date:From; b=ZBe5r40Yhk/+uEKw9MDZPWQYLR812sIdBt0I4VEvEjr5s4wip9r4bAyGu8KG62N93 O9Zn8QyKTKnmDe+S7xZ+Za9KXy1sYgqTCQM2PbzhSK+XPc5/Uu/8IgHONxme+OOuG+ 2xsrfIEuukHuwhJgzDLXsW+O+pLL7Ufzp0g8whoM= Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit From: Michael Meissner To: gcc-cvs@gcc.gnu.org Subject: [gcc(refs/users/meissner/heads/dmf001)] Make changes to make DMF002 branch merge easier. X-Act-Checkin: gcc X-Git-Author: Michael Meissner X-Git-Refname: refs/users/meissner/heads/dmf001 X-Git-Oldrev: 5845184ec534cf4a729a6683c0da1860012da676 X-Git-Newrev: 4a87e1242d7e38712d3c96efceca899472967c60 Message-Id: <20221027033615.75863382A2FF@sourceware.org> Date: Thu, 27 Oct 2022 03:36:15 +0000 (GMT) List-Id: https://gcc.gnu.org/g:4a87e1242d7e38712d3c96efceca899472967c60 commit 4a87e1242d7e38712d3c96efceca899472967c60 Author: Michael Meissner Date: Wed Oct 26 23:35:54 2022 -0400 Make changes to make DMF002 branch merge easier. 2022-10-26 Michael Meissner gcc/ * config/rs6000/constraints.md: Make various changes made in DMF002 branch to make cherry picking changes easier. * config/rs6000/mma.md: Likewise. * config/rs6000/predicates.md: Likewise. * config/rs6000/rs6000-c.cc: Likewise. * config/rs6000/rs6000-call.cc: Likewise. * config/rs6000/rs6000-cpus.def: Likewise. * config/rs6000/rs6000.cc: Likewise. * config/rs6000/rs6000.h: Likewise. * config/rs6000/rs6000.md: Likewise. * config/rs6000/rs6000.opt: Likewise. Diff: --- gcc/config/rs6000/constraints.md | 4 +- gcc/config/rs6000/mma.md | 176 +++++++++++++++++----------------- gcc/config/rs6000/predicates.md | 15 +-- gcc/config/rs6000/rs6000-c.cc | 6 +- gcc/config/rs6000/rs6000-call.cc | 3 +- gcc/config/rs6000/rs6000-cpus.def | 4 +- gcc/config/rs6000/rs6000.cc | 192 +++++++++++++++++++------------------- gcc/config/rs6000/rs6000.h | 18 ++-- gcc/config/rs6000/rs6000.md | 14 +-- gcc/config/rs6000/rs6000.opt | 6 +- 10 files changed, 221 insertions(+), 217 deletions(-) diff --git a/gcc/config/rs6000/constraints.md b/gcc/config/rs6000/constraints.md index af1a0b2c563..5f10057a28a 100644 --- a/gcc/config/rs6000/constraints.md +++ b/gcc/config/rs6000/constraints.md @@ -107,8 +107,8 @@ (match_test "TARGET_P8_VECTOR") (match_operand 0 "s5bit_cint_operand"))) -(define_register_constraint "wD" "DMF_REGS" - "DMF register.") +(define_register_constraint "wD" "DM_REGS" + "Dense math register.") (define_constraint "wE" "@internal Vector constant that can be loaded with the XXSPLTIB instruction." diff --git a/gcc/config/rs6000/mma.md b/gcc/config/rs6000/mma.md index b5fca6ef712..79fe19311d7 100644 --- a/gcc/config/rs6000/mma.md +++ b/gcc/config/rs6000/mma.md @@ -91,10 +91,10 @@ UNSPEC_MMA_XVI8GER4SPP UNSPEC_MMA_XXMFACC UNSPEC_MMA_XXMTACC - UNSPEC_MMA_ASSEMBLE_ACC_DMF - UNSPEC_DMF_INSERT512_UPPER - UNSPEC_DMF_INSERT512_LOWER - UNSPEC_DMF_EXTRACT512 + UNSPEC_DM_ASSEMBLE_ACC + UNSPEC_DM_INSERT512_UPPER + UNSPEC_DM_INSERT512_LOWER + UNSPEC_DM_EXTRACT512 UNSPEC_DMR_RELOAD_FROM_MEMORY UNSPEC_DMR_RELOAD_TO_MEMORY ]) @@ -232,18 +232,18 @@ (define_int_attr vvi4i4i8 [(UNSPEC_MMA_PMXVI4GER8 "pmxvi4ger8")]) -(define_int_attr vvi4i4i8_dmf [(UNSPEC_MMA_PMXVI4GER8 "pmdmxvi4ger8")]) +(define_int_attr vvi4i4i8_dm [(UNSPEC_MMA_PMXVI4GER8 "pmdmxvi4ger8")]) (define_int_attr avvi4i4i8 [(UNSPEC_MMA_PMXVI4GER8PP "pmxvi4ger8pp")]) -(define_int_attr avvi4i4i8_dmf [(UNSPEC_MMA_PMXVI4GER8PP "pmdmxvi4ger8pp")]) +(define_int_attr avvi4i4i8_dm [(UNSPEC_MMA_PMXVI4GER8PP "pmdmxvi4ger8pp")]) (define_int_attr vvi4i4i2 [(UNSPEC_MMA_PMXVI16GER2 "pmxvi16ger2") (UNSPEC_MMA_PMXVI16GER2S "pmxvi16ger2s") (UNSPEC_MMA_PMXVF16GER2 "pmxvf16ger2") (UNSPEC_MMA_PMXVBF16GER2 "pmxvbf16ger2")]) -(define_int_attr vvi4i4i2_dmf [(UNSPEC_MMA_PMXVI16GER2 "pmdmxvi16ger2") +(define_int_attr vvi4i4i2_dm [(UNSPEC_MMA_PMXVI16GER2 "pmdmxvi16ger2") (UNSPEC_MMA_PMXVI16GER2S "pmdmxvi16ger2s") (UNSPEC_MMA_PMXVF16GER2 "pmdmxvf16ger2") (UNSPEC_MMA_PMXVBF16GER2 "pmdmxvbf16ger2")]) @@ -259,7 +259,7 @@ (UNSPEC_MMA_PMXVBF16GER2NP "pmxvbf16ger2np") (UNSPEC_MMA_PMXVBF16GER2NN "pmxvbf16ger2nn")]) -(define_int_attr avvi4i4i2_dmf [(UNSPEC_MMA_PMXVI16GER2PP "pmdmxvi16ger2pp") +(define_int_attr avvi4i4i2_dm [(UNSPEC_MMA_PMXVI16GER2PP "pmdmxvi16ger2pp") (UNSPEC_MMA_PMXVI16GER2SPP "pmdmxvi16ger2spp") (UNSPEC_MMA_PMXVF16GER2PP "pmdmxvf16ger2pp") (UNSPEC_MMA_PMXVF16GER2PN "pmdmxvf16ger2pn") @@ -272,40 +272,40 @@ (define_int_attr vvi4i4 [(UNSPEC_MMA_PMXVF32GER "pmxvf32ger")]) -(define_int_attr vvi4i4_dmf [(UNSPEC_MMA_PMXVF32GER "pmdmxvf32ger")]) +(define_int_attr vvi4i4_dm [(UNSPEC_MMA_PMXVF32GER "pmdmxvf32ger")]) (define_int_attr avvi4i4 [(UNSPEC_MMA_PMXVF32GERPP "pmxvf32gerpp") (UNSPEC_MMA_PMXVF32GERPN "pmxvf32gerpn") (UNSPEC_MMA_PMXVF32GERNP "pmxvf32gernp") (UNSPEC_MMA_PMXVF32GERNN "pmxvf32gernn")]) -(define_int_attr avvi4i4_dmf [(UNSPEC_MMA_PMXVF32GERPP "pmdmxvf32gerpp") +(define_int_attr avvi4i4_dm [(UNSPEC_MMA_PMXVF32GERPP "pmdmxvf32gerpp") (UNSPEC_MMA_PMXVF32GERPN "pmdmxvf32gerpn") (UNSPEC_MMA_PMXVF32GERNP "pmdmxvf32gernp") (UNSPEC_MMA_PMXVF32GERNN "pmdmxvf32gernn")]) (define_int_attr pvi4i2 [(UNSPEC_MMA_PMXVF64GER "pmxvf64ger")]) -(define_int_attr pvi4i2_dmf [(UNSPEC_MMA_PMXVF64GER "pmdmxvf64ger")]) +(define_int_attr pvi4i2_dm [(UNSPEC_MMA_PMXVF64GER "pmdmxvf64ger")]) (define_int_attr apvi4i2 [(UNSPEC_MMA_PMXVF64GERPP "pmxvf64gerpp") (UNSPEC_MMA_PMXVF64GERPN "pmxvf64gerpn") (UNSPEC_MMA_PMXVF64GERNP "pmxvf64gernp") (UNSPEC_MMA_PMXVF64GERNN "pmxvf64gernn")]) -(define_int_attr apvi4i2_dmf [(UNSPEC_MMA_PMXVF64GERPP "pmdmxvf64gerpp") +(define_int_attr apvi4i2_dm [(UNSPEC_MMA_PMXVF64GERPP "pmdmxvf64gerpp") (UNSPEC_MMA_PMXVF64GERPN "pmdmxvf64gerpn") (UNSPEC_MMA_PMXVF64GERNP "pmdmxvf64gernp") (UNSPEC_MMA_PMXVF64GERNN "pmdmxvf64gernn")]) (define_int_attr vvi4i4i4 [(UNSPEC_MMA_PMXVI8GER4 "pmxvi8ger4")]) -(define_int_attr vvi4i4i4_dmf [(UNSPEC_MMA_PMXVI8GER4 "pmdmxvi8ger4")]) +(define_int_attr vvi4i4i4_dm [(UNSPEC_MMA_PMXVI8GER4 "pmdmxvi8ger4")]) (define_int_attr avvi4i4i4 [(UNSPEC_MMA_PMXVI8GER4PP "pmxvi8ger4pp") (UNSPEC_MMA_PMXVI8GER4SPP "pmxvi8ger4spp")]) -(define_int_attr avvi4i4i4_dmf [(UNSPEC_MMA_PMXVI8GER4PP "pmdmxvi8ger4pp") +(define_int_attr avvi4i4i4_dm [(UNSPEC_MMA_PMXVI8GER4PP "pmdmxvi8ger4pp") (UNSPEC_MMA_PMXVI8GER4SPP "pmdmxvi8ger4spp")]) ;; Vector pair support. OOmode can only live in VSRs. @@ -356,7 +356,7 @@ ;; Vector quad support. Under the original MMA, XOmode can only live in FPRs. -;; With DMF, XOmode can live in either VSX registers or DMR registers. +;; With dense math, XOmode can live in either VSX registers or DMR registers. (define_expand "movxo" [(set (match_operand:XO 0 "nonimmediate_operand") (match_operand:XO 1 "input_operand"))] @@ -381,7 +381,7 @@ (define_insn_and_split "*movxo_p10" [(set (match_operand:XO 0 "nonimmediate_operand" "=d,m,d") (match_operand:XO 1 "input_operand" "m,d,d"))] - "TARGET_MMA && !TARGET_DMF + "TARGET_MMA && !TARGET_DENSE_MATH && (gpc_reg_operand (operands[0], XOmode) || gpc_reg_operand (operands[1], XOmode))" "@ @@ -398,10 +398,10 @@ (set_attr "length" "*,*,16") (set_attr "max_prefixed_insns" "2,2,*")]) -(define_insn_and_split "*movxo_dmf" +(define_insn_and_split "*movxo_dm" [(set (match_operand:XO 0 "nonimmediate_operand" "=wa,m, wa,wD,wD,wa") (match_operand:XO 1 "input_operand" "m,wa,wa,wa,wD,wD"))] - "TARGET_DMF + "TARGET_DENSE_MATH && (gpc_reg_operand (operands[0], XOmode) || gpc_reg_operand (operands[1], XOmode))" "@ @@ -412,8 +412,8 @@ dmmr %0,%1 dmxxextfdmr512 %0,%Y0,%1,0" "&& reload_completed - && !dmf_operand (operands[0], XOmode) - && !dmf_operand (operands[1], XOmode)" + && !dmr_operand (operands[0], XOmode) + && !dmr_operand (operands[1], XOmode)" [(const_int 0)] { rs6000_split_multireg_move (operands[0], operands[1]); @@ -503,13 +503,13 @@ rtx op3 = operands[3]; rtx op4 = operands[4]; - if (TARGET_DMF) + if (TARGET_DENSE_MATH) { rtx vpair1 = gen_reg_rtx (OOmode); rtx vpair2 = gen_reg_rtx (OOmode); emit_insn (gen_vsx_assemble_pair (vpair1, op1, op2)); emit_insn (gen_vsx_assemble_pair (vpair2, op3, op4)); - emit_insn (gen_mma_assemble_acc_dmf (op0, vpair1, vpair2)); + emit_insn (gen_mma_assemble_acc_dm (op0, vpair1, vpair2)); } else @@ -529,7 +529,7 @@ (match_operand:V16QI 3 "mma_assemble_input_operand" "mwa") (match_operand:V16QI 4 "mma_assemble_input_operand" "mwa")] UNSPECV_MMA_ASSEMBLE))] - "TARGET_MMA && !TARGET_DMF + "TARGET_MMA && !TARGET_DENSE_MATH && fpr_reg_operand (operands[0], XOmode)" "#" "&& reload_completed" @@ -543,14 +543,14 @@ DONE; }) -;; On a system with DMF, we build the accumulators from two vector pairs. +;; On a system with dense math, we build the accumulators from two vector pairs. -(define_insn "mma_assemble_acc_dmf" - [(set (match_operand:XO 0 "dmf_operand" "=wD") +(define_insn "mma_assemble_acc_dm" + [(set (match_operand:XO 0 "dmr_operand" "=wD") (unspec:XO [(match_operand:OO 1 "vsx_register_operand" "wa") (match_operand:OO 2 "vsx_register_operand" "wa")] - UNSPEC_MMA_ASSEMBLE_ACC_DMF))] - "TARGET_MMA && TARGET_DMF" + UNSPEC_DM_ASSEMBLE_ACC))] + "TARGET_MMA && TARGET_DENSE_MATH" "dmxxinsfdmr512 %0,%1,%2,0" [(set_attr "type" "mma")]) @@ -578,20 +578,20 @@ DONE; }) -(define_insn "*mma_disassemble_acc_dmf" +(define_insn "*mma_disassemble_acc_dm" [(set (match_operand:V16QI 0 "vsx_register_operand" "=wa") - (unspec:V16QI [(match_operand:XO 1 "dmf_operand" "wD") + (unspec:V16QI [(match_operand:XO 1 "dmr_operand" "wD") (match_operand 2 "const_0_to_3_operand")] UNSPEC_MMA_EXTRACT))] - "TARGET_DMF" + "TARGET_DENSE_MATH" "dmxxextfdmr256 %0,%1,2" [(set_attr "type" "mma")]) ;; MMA instructions that do not use their accumulators as an input, still must ;; not allow their vector operands to overlap the registers used by the ;; accumulator. We enforce this by marking the output as early clobber. If we -;; have DMF, we don't need the whole prime/de-prime action, so just make thse -;; instructions be NOPs. +;; have dense math, we don't need the whole prime/de-prime action, so just make +;; thse instructions be NOPs. (define_expand "mma_" [(set (match_operand:XO 0 "register_operand") @@ -599,7 +599,7 @@ MMA_ACC))] "TARGET_MMA" { - if (TARGET_DMF) + if (TARGET_DENSE_MATH) { if (!rtx_equal_p (operands[0], operands[1])) emit_move_insn (operands[0], operands[1]); @@ -613,13 +613,13 @@ [(set (match_operand:XO 0 "fpr_reg_operand" "=&d") (unspec:XO [(match_operand:XO 1 "fpr_reg_operand" "0")] MMA_ACC))] - "TARGET_MMA && !TARGET_DMF" + "TARGET_MMA && !TARGET_DENSE_MATH" " %A0" [(set_attr "type" "mma")]) ;; We can't have integer constants in XOmode so we wrap this in an -;; UNSPEC_VOLATILE for the non-DMF case. For DMF, we don't need to disable -;; optimization and we can do a normal UNSPEC. +;; UNSPEC_VOLATILE for the non-dense math case. For dense math, we don't need +;; to disable optimization and we can do a normal UNSPEC. (define_expand "mma_xxsetaccz" [(set (match_operand:XO 0 "register_operand") @@ -627,9 +627,9 @@ UNSPECV_MMA_XXSETACCZ))] "TARGET_MMA" { - if (TARGET_DMF) + if (TARGET_DENSE_MATH) { - emit_insn (gen_mma_xxsetaccz_dmf (operands[0])); + emit_insn (gen_mma_xxsetaccz_dm (operands[0])); DONE; } }) @@ -638,16 +638,16 @@ [(set (match_operand:XO 0 "fpr_reg_operand" "=d") (unspec_volatile:XO [(const_int 0)] UNSPECV_MMA_XXSETACCZ))] - "TARGET_MMA && !TARGET_DMF" + "TARGET_MMA && !TARGET_DENSE_MATH" "xxsetaccz %A0" [(set_attr "type" "mma")]) -(define_insn "mma_xxsetaccz_dmf" - [(set (match_operand:XO 0 "dmf_operand" "=wD") +(define_insn "mma_xxsetaccz_dm" + [(set (match_operand:XO 0 "dmr_operand" "=wD") (unspec:XO [(const_int 0)] UNSPECV_MMA_XXSETACCZ))] - "TARGET_DMF" + "TARGET_DENSE_MATH" "dmsetaccz %0" [(set_attr "type" "mma")]) @@ -662,7 +662,7 @@ %A0,%x1,%x2 %A0,%x1,%x2" [(set_attr "type" "mma") - (set_attr "isa" "dmf,not_dmf,not_dmf")]) + (set_attr "isa" "dm,not_dm,not_dm")]) (define_insn "mma_" [(set (match_operand:XO 0 "accumulator_operand" "=wD,&d,&d") @@ -673,7 +673,7 @@ "TARGET_MMA" " %A0,%x2,%x3" [(set_attr "type" "mma") - (set_attr "isa" "dmf,not_dmf,not_dmf")]) + (set_attr "isa" "dm,not_dm,not_dm")]) (define_insn "mma_" [(set (match_operand:XO 0 "accumulator_operand" "=wD,&d,&d") @@ -686,7 +686,7 @@ %A0,%x1,%x2 %A0,%x1,%x2" [(set_attr "type" "mma") - (set_attr "isa" "dmf,not_dmf,not_dmf")]) + (set_attr "isa" "dm,not_dm,not_dm")]) (define_insn "mma_" [(set (match_operand:XO 0 "accumulator_operand" "=wD,&d,&d") @@ -700,7 +700,7 @@ %A0,%x2,%x3 %A0,%x2,%x3" [(set_attr "type" "mma") - (set_attr "isa" "dmf,not_dmf,not_dmf")]) + (set_attr "isa" "dm,not_dm,not_dm")]) (define_insn "mma_" [(set (match_operand:XO 0 "accumulator_operand" "=wD,&d,&d") @@ -717,7 +717,7 @@ %A0,%x1,%x2,%3,%4,%5" [(set_attr "type" "mma") (set_attr "prefixed" "yes") - (set_attr "isa" "dmf,not_dmf,not_dmf")]) + (set_attr "isa" "dm,not_dm,not_dm")]) (define_insn "mma_" [(set (match_operand:XO 0 "accumulator_operand" "=wD,&d,&d") @@ -732,7 +732,7 @@ " %A0,%x2,%x3,%4,%5,%6" [(set_attr "type" "mma") (set_attr "prefixed" "yes") - (set_attr "isa" "dmf,not_dmf,not_dmf")]) + (set_attr "isa" "dm,not_dm,not_dm")]) (define_insn "mma_" [(set (match_operand:XO 0 "accumulator_operand" "=wD,&d,&d") @@ -744,12 +744,12 @@ MMA_VVI4I4I2))] "TARGET_MMA" "@ - %A0,%x1,%x2,%3,%4,%5 + %A0,%x1,%x2,%3,%4,%5 %A0,%x1,%x2,%3,%4,%5 %A0,%x1,%x2,%3,%4,%5" [(set_attr "type" "mma") (set_attr "prefixed" "yes") - (set_attr "isa" "dmf,not_dmf,not_dmf")]) + (set_attr "isa" "dm,not_dm,not_dm")]) (define_insn "mma_" [(set (match_operand:XO 0 "accumulator_operand" "=wD,&d,&d") @@ -762,12 +762,12 @@ MMA_AVVI4I4I2))] "TARGET_MMA" "@ - %A0,%x2,%x3,%4,%5,%6 + %A0,%x2,%x3,%4,%5,%6 %A0,%x2,%x3,%4,%5,%6 %A0,%x2,%x3,%4,%5,%6" [(set_attr "type" "mma") (set_attr "prefixed" "yes") - (set_attr "isa" "dmf,not_dmf,not_dmf")]) + (set_attr "isa" "dm,not_dm,not_dm")]) (define_insn "mma_" [(set (match_operand:XO 0 "accumulator_operand" "=wD,&d,&d") @@ -778,12 +778,12 @@ MMA_VVI4I4))] "TARGET_MMA" "@ - %A0,%x1,%x2,%3,%4 + %A0,%x1,%x2,%3,%4 %A0,%x1,%x2,%3,%4 %A0,%x1,%x2,%3,%4" [(set_attr "type" "mma") (set_attr "prefixed" "yes") - (set_attr "isa" "dmf,not_dmf,not_dmf")]) + (set_attr "isa" "dm,not_dm,not_dm")]) (define_insn "mma_" [(set (match_operand:XO 0 "accumulator_operand" "=wD,&d,&d") @@ -795,12 +795,12 @@ MMA_AVVI4I4))] "TARGET_MMA" "@ - %A0,%x2,%x3,%4,%5 + %A0,%x2,%x3,%4,%5 %A0,%x2,%x3,%4,%5 %A0,%x2,%x3,%4,%5" [(set_attr "type" "mma") (set_attr "prefixed" "yes") - (set_attr "isa" "dmf,not_dmf,not_dmf")]) + (set_attr "isa" "dm,not_dm,not_dm")]) (define_insn "mma_" [(set (match_operand:XO 0 "accumulator_operand" "=wD,&d,&d") @@ -811,12 +811,12 @@ MMA_PVI4I2))] "TARGET_MMA" "@ - %A0,%x1,%x2,%3,%4 + %A0,%x1,%x2,%3,%4 %A0,%x1,%x2,%3,%4 %A0,%x1,%x2,%3,%4" [(set_attr "type" "mma") (set_attr "prefixed" "yes") - (set_attr "isa" "dmf,not_dmf,not_dmf")]) + (set_attr "isa" "dm,not_dm,not_dm")]) (define_insn "mma_" [(set (match_operand:XO 0 "accumulator_operand" "=wD,&d,&d") @@ -828,12 +828,12 @@ MMA_APVI4I2))] "TARGET_MMA" "@ - %A0,%x2,%x3,%4,%5 + %A0,%x2,%x3,%4,%5 %A0,%x2,%x3,%4,%5 %A0,%x2,%x3,%4,%5" [(set_attr "type" "mma") (set_attr "prefixed" "yes") - (set_attr "isa" "dmf,not_dmf,not_dmf")]) + (set_attr "isa" "dm,not_dm,not_dm")]) (define_insn "mma_" [(set (match_operand:XO 0 "accumulator_operand" "=wD,&d,&d") @@ -845,12 +845,12 @@ MMA_VVI4I4I4))] "TARGET_MMA" "@ - %A0,%x1,%x2,%3,%4,%5 + %A0,%x1,%x2,%3,%4,%5 %A0,%x1,%x2,%3,%4,%5 %A0,%x1,%x2,%3,%4,%5" [(set_attr "type" "mma") (set_attr "prefixed" "yes") - (set_attr "isa" "dmf,not_dmf,not_dmf")]) + (set_attr "isa" "dm,not_dm,not_dm")]) (define_insn "mma_" [(set (match_operand:XO 0 "accumulator_operand" "=wD,&d,&d") @@ -863,19 +863,19 @@ MMA_AVVI4I4I4))] "TARGET_MMA" "@ - %A0,%x2,%x3,%4,%5,%6 + %A0,%x2,%x3,%4,%5,%6 %A0,%x2,%x3,%4,%5,%6 %A0,%x2,%x3,%4,%5,%6" [(set_attr "type" "mma") (set_attr "prefixed" "yes") - (set_attr "isa" "dmf,not_dmf,not_dmf")]) + (set_attr "isa" "dm,not_dm,not_dm")]) ;; TDOmode (i.e. __dmr). (define_expand "movtdo" [(set (match_operand:TDO 0 "nonimmediate_operand") (match_operand:TDO 1 "input_operand"))] - "TARGET_DMF" + "TARGET_DENSE_MATH" { rs6000_emit_move (operands[0], operands[1], TDOmode); DONE; @@ -884,7 +884,7 @@ (define_insn_and_split "*movtdo" [(set (match_operand:TDO 0 "nonimmediate_operand" "=wa,m,wa,wD,wD,wa") (match_operand:TDO 1 "input_operand" "m,wa,wa,wa,wD,wD"))] - "TARGET_DMF + "TARGET_DENSE_MATH && (gpc_reg_operand (operands[0], TDOmode) || gpc_reg_operand (operands[1], TDOmode))" "@ @@ -895,7 +895,7 @@ dmmr %0,%1 #" "&& reload_completed - && (!dmf_operand (operands[0], TDOmode) || !dmf_operand (operands[1], TDOmode))" + && (!dmr_operand (operands[0], TDOmode) || !dmr_operand (operands[1], TDOmode))" [(const_int 0)] { rtx op0 = operands[0]; @@ -906,7 +906,7 @@ int regno0 = REGNO (op0); int regno1 = REGNO (op1); - if (DMF_REGNO_P (regno0) && VSX_REGNO_P (regno1)) + if (DMR_REGNO_P (regno0) && VSX_REGNO_P (regno1)) { rtx op1_upper = gen_rtx_REG (XOmode, regno1); rtx op1_lower = gen_rtx_REG (XOmode, regno1 + 4); @@ -915,7 +915,7 @@ DONE; } - else if (VSX_REGNO_P (regno0) && DMF_REGNO_P (regno1)) + else if (VSX_REGNO_P (regno0) && DMR_REGNO_P (regno1)) { rtx op0_upper = gen_rtx_REG (XOmode, regno0); rtx op0_lower = gen_rtx_REG (XOmode, regno0 + 4); @@ -935,19 +935,19 @@ ;; Move from VSX registers to DMR registers via two insert 512 bit ;; instructions. (define_insn "movtdo_insert512_upper" - [(set (match_operand:TDO 0 "dmf_operand" "=wD") + [(set (match_operand:TDO 0 "dmr_operand" "=wD") (unspec:TDO [(match_operand:XO 1 "vsx_register_operand" "wa")] - UNSPEC_DMF_INSERT512_UPPER))] - "TARGET_DMF" + UNSPEC_DM_INSERT512_UPPER))] + "TARGET_DENSE_MATH" "dmxxinstdmr512 %0,%1,%Y1,0" [(set_attr "type" "mma")]) (define_insn "movtdo_insert512_lower" - [(set (match_operand:TDO 0 "dmf_operand" "=wD") - (unspec:TDO [(match_operand:TDO 1 "dmf_operand" "0") + [(set (match_operand:TDO 0 "dmr_operand" "=wD") + (unspec:TDO [(match_operand:TDO 1 "dmr_operand" "0") (match_operand:XO 2 "vsx_register_operand" "wa")] - UNSPEC_DMF_INSERT512_LOWER))] - "TARGET_DMF" + UNSPEC_DM_INSERT512_LOWER))] + "TARGET_DENSE_MATH" "dmxxinstdmr512 %0,%2,%Y2,1" [(set_attr "type" "mma")]) @@ -955,20 +955,20 @@ ;; instructions. (define_insn "movtdo_extract512" [(set (match_operand:XO 0 "vsx_register_operand" "=wa") - (unspec:XO [(match_operand:TDO 1 "dmf_operand" "wD") + (unspec:XO [(match_operand:TDO 1 "dmr_operand" "wD") (match_operand 2 "const_0_to_1_operand" "n")] - UNSPEC_DMF_EXTRACT512))] - "TARGET_DMF" + UNSPEC_DM_EXTRACT512))] + "TARGET_DENSE_MATH" "dmxxextfdmr512 %0,%Y0,%1,%2" [(set_attr "type" "mma")]) -;; Reload DMF registers from memory -(define_insn_and_split "reload_dmf_from_memory" - [(set (match_operand:TDO 0 "dmf_operand" "=wD") +;; Reload DMR registers from memory +(define_insn_and_split "reload_dmr_from_memory" + [(set (match_operand:TDO 0 "dmr_operand" "=wD") (unspec:TDO [(match_operand:TDO 1 "memory_operand" "m")] UNSPEC_DMR_RELOAD_FROM_MEMORY)) (clobber (match_operand:XO 2 "vsx_register_operand" "=wa"))] - "TARGET_DMF" + "TARGET_DENSE_MATH" "#" "&& reload_completed" [(const_int 0)] @@ -990,13 +990,13 @@ (set_attr "max_prefixed_insns" "2") (set_attr "type" "vecload")]) -;; Reload DMF registers to memory -(define_insn_and_split "reload_dmf_to_memory" +;; Reload dense math registers to memory +(define_insn_and_split "reload_dmr_to_memory" [(set (match_operand:TDO 0 "memory_operand" "=m") - (unspec:TDO [(match_operand:TDO 1 "dmf_operand" "wD")] + (unspec:TDO [(match_operand:TDO 1 "dmr_operand" "wD")] UNSPEC_DMR_RELOAD_TO_MEMORY)) (clobber (match_operand:XO 2 "vsx_register_operand" "=wa"))] - "TARGET_DMF" + "TARGET_DENSE_MATH" "#" "&& reload_completed" [(const_int 0)] diff --git a/gcc/config/rs6000/predicates.md b/gcc/config/rs6000/predicates.md index 5fcda8543b2..0ba02f1c15d 100644 --- a/gcc/config/rs6000/predicates.md +++ b/gcc/config/rs6000/predicates.md @@ -186,8 +186,8 @@ return VLOGICAL_REGNO_P (REGNO (op)); }) -;; Return 1 if op is a DMF register -(define_predicate "dmf_operand" +;; Return 1 if op is a dense math register +(define_predicate "dmr_operand" (match_operand 0 "register_operand") { if (!REG_P (op)) @@ -196,12 +196,13 @@ if (!HARD_REGISTER_P (op)) return 1; - return DMF_REGNO_P (REGNO (op)); + return DMR_REGNO_P (REGNO (op)); }) ;; Return 1 if op is an accumulator. On power10 systems, the accumulators -;; overlap with the FPRs, while on systems with DMF, the accumulators are -;; separate dense math registers and do not overlap with the FPR registers.. +;; overlap with the FPRs, while on systems with dense math, the accumulators +;; are separate dense math registers and do not overlap with the FPR +;; registers.. (define_predicate "accumulator_operand" (match_operand 0 "register_operand") { @@ -212,8 +213,8 @@ return 1; int r = REGNO (op); - return (TARGET_DMF - ? DMF_REGNO_P (r) + return (TARGET_DENSE_MATH + ? DMR_REGNO_P (r) : FP_REGNO_P (r) && (r & 3) == 0); }) diff --git a/gcc/config/rs6000/rs6000-c.cc b/gcc/config/rs6000/rs6000-c.cc index 0a0e4bcd618..c1ff3c815f9 100644 --- a/gcc/config/rs6000/rs6000-c.cc +++ b/gcc/config/rs6000/rs6000-c.cc @@ -598,9 +598,9 @@ rs6000_target_modify_macros (bool define_p, HOST_WIDE_INT flags) /* Tell the user if we support the MMA instructions. */ if ((flags & OPTION_MASK_MMA) != 0) rs6000_define_or_undefine_macro (define_p, "__MMA__"); - /* Tell the user if we support the DMF instructions. */ - if ((flags & OPTION_MASK_DMF) != 0) - rs6000_define_or_undefine_macro (define_p, "__DMF__"); + /* Tell the user if we support the dense math instructions. */ + if ((flags & OPTION_MASK_DENSE_MATH) != 0) + rs6000_define_or_undefine_macro (define_p, "__DENSE_MATH__"); /* Whether pc-relative code is being generated. */ if ((flags & OPTION_MASK_PCREL) != 0) rs6000_define_or_undefine_macro (define_p, "__PCREL__"); diff --git a/gcc/config/rs6000/rs6000-call.cc b/gcc/config/rs6000/rs6000-call.cc index aa08183c8b6..b2de6b84d09 100644 --- a/gcc/config/rs6000/rs6000-call.cc +++ b/gcc/config/rs6000/rs6000-call.cc @@ -1646,7 +1646,8 @@ rs6000_function_arg (cumulative_args_t cum_v, const function_arg_info &arg) { if (TYPE_CANONICAL (type) != NULL_TREE) type = TYPE_CANONICAL (type); - error ("invalid use of DMF operand of type %qs as a function parameter", + error ("invalid use of dense math operand of type %qs as a function " + "parameter", IDENTIFIER_POINTER (DECL_NAME (TYPE_NAME (type)))); return NULL_RTX; } diff --git a/gcc/config/rs6000/rs6000-cpus.def b/gcc/config/rs6000/rs6000-cpus.def index c6e545ca71e..f2419dad5cb 100644 --- a/gcc/config/rs6000/rs6000-cpus.def +++ b/gcc/config/rs6000/rs6000-cpus.def @@ -90,7 +90,7 @@ /* Flags for a potential future processor that may or may not be delivered. */ #define ISA_FUTURE_MASKS (ISA_3_1_MASKS_SERVER \ | OPTION_MASK_BLOCK_OPS_VECTOR_PAIR \ - | OPTION_MASK_DMF) + | OPTION_MASK_DENSE_MATH) /* Flags that need to be turned off if -mno-power9-vector. */ #define OTHER_P9_VECTOR_MASKS (OPTION_MASK_FLOAT128_HW \ @@ -133,7 +133,7 @@ | OPTION_MASK_DFP \ | OPTION_MASK_DIRECT_MOVE \ | OPTION_MASK_DLMZB \ - | OPTION_MASK_DMF \ + | OPTION_MASK_DENSE_MATH \ | OPTION_MASK_EFFICIENT_UNALIGNED_VSX \ | OPTION_MASK_FLOAT128_HW \ | OPTION_MASK_FLOAT128_KEYWORD \ diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc index dc1649b601a..9e7c88086a7 100644 --- a/gcc/config/rs6000/rs6000.cc +++ b/gcc/config/rs6000/rs6000.cc @@ -291,7 +291,7 @@ enum rs6000_reg_type { FPR_REG_TYPE, SPR_REG_TYPE, CR_REG_TYPE, - DMF_REG_TYPE + DM_REG_TYPE }; /* Map register class to register type. */ @@ -305,15 +305,15 @@ static enum rs6000_reg_type reg_class_to_reg_type[N_REG_CLASSES]; /* Register classes we care about in secondary reload or go if legitimate - address. We only need to worry about GPR, FPR, Altivec, and DMF registers + address. We only need to worry about GPR, FPR, Altivec, and DMR registers here, along an ANY field that is the OR of the 4 register classes. */ enum rs6000_reload_reg_type { RELOAD_REG_GPR, /* General purpose registers. */ RELOAD_REG_FPR, /* Traditional floating point regs. */ RELOAD_REG_VMX, /* Altivec (VMX) registers. */ - RELOAD_REG_DMF, /* DMF registers. */ - RELOAD_REG_ANY, /* OR of GPR/FPR/VMX/DMF masks. */ + RELOAD_REG_DMR, /* DMR registers. */ + RELOAD_REG_ANY, /* OR of GPR/FPR/VMX/DMR masks. */ N_RELOAD_REG }; @@ -321,7 +321,7 @@ enum rs6000_reload_reg_type { into real registers, and skip the ANY class, which is just an OR of the bits. */ #define FIRST_RELOAD_REG_CLASS RELOAD_REG_GPR -#define LAST_RELOAD_REG_CLASS RELOAD_REG_DMF +#define LAST_RELOAD_REG_CLASS RELOAD_REG_DMR /* Map reload register type to a register in the register class. */ struct reload_reg_map_type { @@ -333,7 +333,7 @@ static const struct reload_reg_map_type reload_reg_map[N_RELOAD_REG] = { { "Gpr", FIRST_GPR_REGNO }, /* RELOAD_REG_GPR. */ { "Fpr", FIRST_FPR_REGNO }, /* RELOAD_REG_FPR. */ { "VMX", FIRST_ALTIVEC_REGNO }, /* RELOAD_REG_VMX. */ - { "DMF", FIRST_DMF_REGNO }, /* RELOAD_REG_DMF. */ + { "DMR", FIRST_DMR_REGNO }, /* RELOAD_REG_DMR. */ { "Any", -1 }, /* RELOAD_REG_ANY. */ }; @@ -1227,7 +1227,7 @@ char rs6000_reg_names[][8] = "0", "1", "2", "3", "4", "5", "6", "7", /* vrsave vscr sfp */ "vrsave", "vscr", "sfp", - /* DMFs */ + /* DMRs */ "0", "1", "2", "3", "4", "5", "6", "7", }; @@ -1255,7 +1255,7 @@ static const char alt_reg_names[][8] = "%cr0", "%cr1", "%cr2", "%cr3", "%cr4", "%cr5", "%cr6", "%cr7", /* vrsave vscr sfp */ "vrsave", "vscr", "sfp", - /* DMFs */ + /* DMRs */ "%dmr0", "%dmr1", "%dmr2", "%dmr3", "%dmr4", "%dmr5", "%dmr6", "%dmr7", }; #endif @@ -1830,8 +1830,8 @@ rs6000_hard_regno_nregs_internal (int regno, machine_mode mode) else if (ALTIVEC_REGNO_P (regno)) reg_size = UNITS_PER_ALTIVEC_WORD; - else if (DMF_REGNO_P (regno)) - reg_size = UNITS_PER_DMF_WORD; + else if (DMR_REGNO_P (regno)) + reg_size = UNITS_PER_DMR_WORD; else reg_size = UNITS_PER_WORD; @@ -1856,17 +1856,17 @@ rs6000_hard_regno_mode_ok_uncached (int regno, machine_mode mode) /* On power10, MMA accumulator modes need FPR registers divisible by 4. - If DMF is enabled, allow all VSX registers plus the DMF registers. We - need to make sure we don't cross between the boundary of FPRs and - traditional Altiviec registers. */ + If dense math is enabled, allow all VSX registers plus the dense math + registers. We need to make sure we don't cross between the boundary of + FPRs and traditional Altiviec registers. */ if (mode == XOmode) { - if (TARGET_MMA && !TARGET_DMF) + if (TARGET_MMA && !TARGET_DENSE_MATH) return (FP_REGNO_P (regno) && (regno & 3) == 0); - else if (TARGET_DMF) + else if (TARGET_DENSE_MATH) { - if (DMF_REGNO_P (regno)) + if (DMR_REGNO_P (regno)) return 1; if (FP_REGNO_P (regno)) @@ -1880,15 +1880,15 @@ rs6000_hard_regno_mode_ok_uncached (int regno, machine_mode mode) return 0; } - /* DMF register modes need DMF registers or VSX registers divisible by 2. We - need to make sure we don't cross between the boundary of FPRs and + /* Dense math register modes need DMR registers or VSX registers divisible by + 2. We need to make sure we don't cross between the boundary of FPRs and traditional Altiviec registers. */ if (mode == TDOmode) { - if (!TARGET_DMF) + if (!TARGET_DENSE_MATH) return 0; - if (DMF_REGNO_P (regno)) + if (DMR_REGNO_P (regno)) return 1; if (FP_REGNO_P (regno)) @@ -1900,8 +1900,8 @@ rs6000_hard_regno_mode_ok_uncached (int regno, machine_mode mode) return 0; } - /* No other types other than XOmode or TDOmode can go in DMFs. */ - if (DMF_REGNO_P (regno)) + /* No other types other than XOmode or TDOmode can go in DMRs. */ + if (DMR_REGNO_P (regno)) return 0; /* PTImode can only go in GPRs. Quad word memory operations require even/odd @@ -2010,9 +2010,9 @@ rs6000_hard_regno_mode_ok (unsigned int regno, machine_mode mode) Similarly, don't allow OOmode (vector pair), XOmode (vector quad), or TDOmode (dmr register) to pair with anything else. Vector pairs are - restricted to even/odd VSX registers. Without DMF, vector quads are limited - to FPR registers divisible by 4. With DMF, vector quads are limited to even - VSX registers or DMR registers. + restricted to even/odd VSX registers. Without dense math, vector quads are + limited to FPR registers divisible by 4. With dense math, vector quads are + limited to even VSX registers or DMR registers. Altivec/VSX vector tests were moved ahead of scalar float mode, so that IEEE 128-bit floating point on VSX systems ties with other vectors. */ @@ -2354,7 +2354,7 @@ rs6000_debug_reg_global (void) rs6000_debug_reg_print (FIRST_ALTIVEC_REGNO, LAST_ALTIVEC_REGNO, "vs"); - rs6000_debug_reg_print (FIRST_DMF_REGNO, LAST_DMF_REGNO, "dmf"); + rs6000_debug_reg_print (FIRST_DMR_REGNO, LAST_DMR_REGNO, "dmr"); rs6000_debug_reg_print (LR_REGNO, LR_REGNO, "lr"); rs6000_debug_reg_print (CTR_REGNO, CTR_REGNO, "ctr"); rs6000_debug_reg_print (CR0_REGNO, CR7_REGNO, "cr"); @@ -2679,10 +2679,10 @@ rs6000_setup_reg_addr_masks (void) addr_mask = 0; reg = reload_reg_map[rc].reg; - /* Special case DMF registers. */ - if (rc == RELOAD_REG_DMF) + /* Special case DMR registers. */ + if (rc == RELOAD_REG_DMR) { - if (TARGET_DMF && (m2 == XOmode || m2 == TDOmode)) + if (TARGET_DENSE_MATH && (m2 == XOmode || m2 == TDOmode)) { addr_mask = RELOAD_REG_VALID | RELOAD_REG_NO_MEMORY; reg_addr[m].addr_mask[rc] = addr_mask; @@ -2844,8 +2844,8 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p) for (r = CR1_REGNO; r <= CR7_REGNO; ++r) rs6000_regno_regclass[r] = CR_REGS; - for (r = FIRST_DMF_REGNO; r <= LAST_DMF_REGNO; ++r) - rs6000_regno_regclass[r] = DMF_REGS; + for (r = FIRST_DMR_REGNO; r <= LAST_DMR_REGNO; ++r) + rs6000_regno_regclass[r] = DM_REGS; rs6000_regno_regclass[LR_REGNO] = LINK_REGS; rs6000_regno_regclass[CTR_REGNO] = CTR_REGS; @@ -2871,7 +2871,7 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p) reg_class_to_reg_type[(int)LINK_OR_CTR_REGS] = SPR_REG_TYPE; reg_class_to_reg_type[(int)CR_REGS] = CR_REG_TYPE; reg_class_to_reg_type[(int)CR0_REGS] = CR_REG_TYPE; - reg_class_to_reg_type[(int)DMF_REGS] = DMF_REG_TYPE; + reg_class_to_reg_type[(int)DM_REGS] = DM_REG_TYPE; if (TARGET_VSX) { @@ -3021,7 +3021,7 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p) } /* Add support for 1,024 bit DMR registers. */ - if (TARGET_DMF) + if (TARGET_DENSE_MATH) { rs6000_vector_unit[TDOmode] = VECTOR_NONE; rs6000_vector_mem[TDOmode] = VECTOR_VSX; @@ -3234,10 +3234,10 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p) } } - if (TARGET_DMF) + if (TARGET_DENSE_MATH) { - reg_addr[TDOmode].reload_load = CODE_FOR_reload_dmf_from_memory; - reg_addr[TDOmode].reload_store = CODE_FOR_reload_dmf_to_memory; + reg_addr[TDOmode].reload_load = CODE_FOR_reload_dmr_from_memory; + reg_addr[TDOmode].reload_store = CODE_FOR_reload_dmr_to_memory; } /* Precalculate HARD_REGNO_NREGS. */ @@ -4501,12 +4501,12 @@ rs6000_option_override_internal (bool global_init_p) if (!TARGET_PCREL && TARGET_PCREL_OPT) rs6000_isa_flags &= ~OPTION_MASK_PCREL_OPT; - /* DMF requires MMA. */ - if (TARGET_DMF && !TARGET_MMA) + /* Dense math requires MMA. */ + if (TARGET_DENSE_MATH && !TARGET_MMA) { - if ((rs6000_isa_flags_explicit & OPTION_MASK_DMF) != 0) - error ("%qs requires %qs", "-mdmf", "-mmma"); - rs6000_isa_flags &= ~OPTION_MASK_DMF; + if ((rs6000_isa_flags_explicit & OPTION_MASK_DENSE_MATH) != 0) + error ("%qs requires %qs", "-mdense-math", "-mmma"); + rs6000_isa_flags &= ~OPTION_MASK_DENSE_MATH; } if (TARGET_DEBUG_REG || TARGET_DEBUG_TARGET) @@ -8729,14 +8729,14 @@ reg_offset_addressing_ok_p (machine_mode mode) return mode_supports_dq_form (mode); break; - /* The vector pair/quad types and the DMF types support offset addressing - if the underlying vectors support offset addressing. */ + /* The vector pair/quad types and the dense math types support offset + addressing if the underlying vectors support offset addressing. */ case E_OOmode: case E_XOmode: return TARGET_MMA; case E_TDOmode: - return TARGET_DMF; + return TARGET_DENSE_MATH; case E_SDmode: /* If we can do direct load/stores of SDmode, restrict it to reg+reg @@ -12186,7 +12186,7 @@ rs6000_secondary_reload_memory (rtx addr, /* DMR registers use VSX registers, and need to generate some extra instructions. */ - else if (rclass == DMF_REGS) + else if (rclass == DM_REGS) return 2; /* If the register allocator hasn't made up its mind yet on the register @@ -12519,9 +12519,9 @@ rs6000_secondary_reload_simple_move (enum rs6000_reg_type to_type, /* We can transfer between VSX registers and DMR registers without needing extra registers. */ - if (TARGET_DMF && (mode == XOmode || mode == TDOmode) - && ((to_type == DMF_REG_TYPE && from_type == VSX_REG_TYPE) - || (to_type == VSX_REG_TYPE && from_type == DMF_REG_TYPE))) + if (TARGET_DENSE_MATH && (mode == XOmode || mode == TDOmode) + && ((to_type == DM_REG_TYPE && from_type == VSX_REG_TYPE) + || (to_type == VSX_REG_TYPE && from_type == DM_REG_TYPE))) return true; return false; @@ -13218,8 +13218,8 @@ rs6000_preferred_reload_class (rtx x, enum reg_class rclass) machine_mode mode = GET_MODE (x); bool is_constant = CONSTANT_P (x); - /* DMF registers can't be loaded or stored. */ - if (rclass == DMF_REGS) + /* DMR registers can't be loaded or stored. */ + if (rclass == DM_REGS) return NO_REGS; /* If a mode can't go in FPR/ALTIVEC/VSX registers, don't return a preferred @@ -13318,7 +13318,7 @@ rs6000_preferred_reload_class (rtx x, enum reg_class rclass) return VSX_REGS; if (mode == XOmode) - return TARGET_DMF ? VSX_REGS : FLOAT_REGS; + return TARGET_DENSE_MATH ? VSX_REGS : FLOAT_REGS; if (mode == TDOmode) return VSX_REGS; @@ -13446,9 +13446,10 @@ rs6000_secondary_reload_class (enum reg_class rclass, machine_mode mode, else regno = -1; - /* DMF registers don't have loads or stores. We have to go through the VSX - registers to load XOmode (vector quad) and TDOmode (dmf 1024 bit). */ - if (TARGET_DMF && rclass == DMF_REGS) + /* Dense math registers don't have loads or stores. We have to go through + the VSX registers to load XOmode (vector quad) and TDOmode (dmr 1024 + bit). */ + if (TARGET_DENSE_MATH && rclass == DM_REGS) return VSX_REGS; /* If we have VSX register moves, prefer moving scalar values between @@ -13965,14 +13966,14 @@ print_operand (FILE *file, rtx x, int code) case 'A': /* Write the MMA accumulator number associated with VSX register X. On - DMF systems, only allow DMF accumulators, not accumulators overlapping - with the FPR registers. */ + dense math systems, only allow DMR accumulators, not accumulators + overlapping with the FPR registers. */ if (!REG_P (x)) output_operand_lossage ("invalid %%A value"); - else if (TARGET_DMF) + else if (TARGET_DENSE_MATH) { - if (DMF_REGNO_P (REGNO (x))) - fprintf (file, "%d", REGNO (x) - FIRST_DMF_REGNO); + if (DMR_REGNO_P (REGNO (x))) + fprintf (file, "%d", REGNO (x) - FIRST_DMR_REGNO); else output_operand_lossage ("%%A operand is not a DMR"); } @@ -22580,19 +22581,19 @@ rs6000_debug_address_cost (rtx x, machine_mode mode, } -/* Subroutine to determine the move cost of DMF registers. If we are moving - to/from VSX_REGISTER registers, the cost is either 1 move (for 512-bit - accumulators) or 2 moves (for 1,024 dmr registers). If we are moving to - anything else like GPR registers, make the cost very high. */ +/* Subroutine to determine the move cost of dense math registers. If we are + moving to/from VSX_REGISTER registers, the cost is either 1 move (for + 512-bit accumulators) or 2 moves (for 1,024 dmr registers). If we are + moving to anything else like GPR registers, make the cost very high. */ static int -rs6000_dmf_register_move_cost (machine_mode mode, reg_class_t rclass) +rs6000_dmr_register_move_cost (machine_mode mode, reg_class_t rclass) { const int reg_move_base = 2; HARD_REG_SET vsx_set = (reg_class_contents[rclass] & reg_class_contents[VSX_REGS]); - if (TARGET_DMF && !hard_reg_set_empty_p (vsx_set)) + if (TARGET_DENSE_MATH && !hard_reg_set_empty_p (vsx_set)) { /* __vector_quad (i.e. XOmode) is tranfered in 1 instruction. */ if (mode == XOmode) @@ -22603,10 +22604,10 @@ rs6000_dmf_register_move_cost (machine_mode mode, reg_class_t rclass) return reg_move_base * 2; else - return reg_move_base * 2 * hard_regno_nregs (FIRST_DMF_REGNO, mode); + return reg_move_base * 2 * hard_regno_nregs (FIRST_DMR_REGNO, mode); } - return 1000 * 2 * hard_regno_nregs (FIRST_DMF_REGNO, mode); + return 1000 * 2 * hard_regno_nregs (FIRST_DMR_REGNO, mode); } /* A C expression returning the cost of moving data from a register of class @@ -22627,14 +22628,14 @@ rs6000_register_move_cost (machine_mode mode, from_vsx = reg_class_contents[from] & reg_class_contents[VSX_REGS]; /* Special case DMR registers, that can only move to/from VSX registers. */ - if (from == DMF_REGS && to == DMF_REGS) - ret = 2 * hard_regno_nregs (FIRST_DMF_REGNO, mode); + if (from == DM_REGS && to == DM_REGS) + ret = 2 * hard_regno_nregs (FIRST_DMR_REGNO, mode); - else if (from == DMF_REGS) - ret = rs6000_dmf_register_move_cost (mode, to); + else if (from == DM_REGS) + ret = rs6000_dmr_register_move_cost (mode, to); - else if (to == DMF_REGS) - ret = rs6000_dmf_register_move_cost (mode, from); + else if (to == DM_REGS) + ret = rs6000_dmr_register_move_cost (mode, from); /* If we have VSX, we can easily move between FPR or Altivec registers, otherwise we can only easily move within classes. @@ -22739,8 +22740,8 @@ rs6000_memory_move_cost (machine_mode mode, reg_class_t rclass, ret = 4 * hard_regno_nregs (32, mode); else if (reg_classes_intersect_p (rclass, ALTIVEC_REGS)) ret = 4 * hard_regno_nregs (FIRST_ALTIVEC_REGNO, mode); - else if (reg_classes_intersect_p (rclass, DMF_REGS)) - ret = (rs6000_dmf_register_move_cost (mode, VSX_REGS) + else if (reg_classes_intersect_p (rclass, DM_REGS)) + ret = (rs6000_dmr_register_move_cost (mode, VSX_REGS) + rs6000_memory_move_cost (mode, VSX_REGS, false)); else ret = 4 + rs6000_register_move_cost (mode, rclass, GENERAL_REGS); @@ -23950,8 +23951,8 @@ rs6000_compute_pressure_classes (enum reg_class *pressure_classes) if (TARGET_HARD_FLOAT) pressure_classes[n++] = FLOAT_REGS; } - if (TARGET_DMF) - pressure_classes[n++] = DMF_REGS; + if (TARGET_DENSE_MATH) + pressure_classes[n++] = DM_REGS; pressure_classes[n++] = CR_REGS; pressure_classes[n++] = SPECIAL_REGS; @@ -24116,10 +24117,10 @@ rs6000_debugger_regno (unsigned int regno, unsigned int format) return 67; if (regno == 64) return 64; - /* XXX: This is a guess. The GCC register number for FIRST_DMF_REGNO is 111, + /* XXX: This is a guess. The GCC register number for FIRST_DMR_REGNO is 111, but the frame pointer regnum above uses that. */ - if (DMF_REGNO_P (regno)) - return regno - FIRST_DMF_REGNO + 112; + if (DMR_REGNO_P (regno)) + return regno - FIRST_DMR_REGNO + 112; gcc_unreachable (); } @@ -24330,7 +24331,7 @@ static struct rs6000_opt_mask const rs6000_opt_masks[] = { "crypto", OPTION_MASK_CRYPTO, false, true }, { "direct-move", OPTION_MASK_DIRECT_MOVE, false, true }, { "dlmzb", OPTION_MASK_DLMZB, false, true }, - { "dmf", OPTION_MASK_DMF, false, true }, + { "dense-math", OPTION_MASK_DENSE_MATH, false, true }, { "efficient-unaligned-vsx", OPTION_MASK_EFFICIENT_UNALIGNED_VSX, false, true }, { "float128", OPTION_MASK_FLOAT128_KEYWORD, false, true }, @@ -27296,8 +27297,9 @@ rs6000_split_multireg_move (rtx dst, rtx src) mode = GET_MODE (dst); nregs = hard_regno_nregs (reg, mode); - /* If we have a vector quad register for MMA or DMR register for DMF, and - this is a load or store, see if we can use vector paired load/stores. */ + /* If we have a vector quad register for MMA or DMR register for dense math, + and this is a load or store, see if we can use vector paired + load/stores. */ if ((mode == XOmode || mode == TDOmode) && TARGET_MMA && (MEM_P (dst) || MEM_P (src))) { @@ -27369,7 +27371,7 @@ rs6000_split_multireg_move (rtx dst, rtx src) /* If we are reading an accumulator register, we have to deprime it before we can access it. */ - if (TARGET_MMA && !TARGET_DMF + if (TARGET_MMA && !TARGET_DENSE_MATH && GET_MODE (src) == XOmode && FP_REGNO_P (REGNO (src))) emit_insn (gen_mma_xxmfacc (src, src)); @@ -27403,7 +27405,7 @@ rs6000_split_multireg_move (rtx dst, rtx src) /* If we are writing an accumulator register that overlaps with the FPR registers, we have to prime it after we've written it. */ - if (TARGET_MMA && !TARGET_DMF + if (TARGET_MMA && !TARGET_DENSE_MATH && GET_MODE (dst) == XOmode && FP_REGNO_P (REGNO (dst))) emit_insn (gen_mma_xxmtacc (dst, dst)); @@ -27417,7 +27419,7 @@ rs6000_split_multireg_move (rtx dst, rtx src) || XINT (src, 1) == UNSPECV_MMA_ASSEMBLE); gcc_assert (REG_P (dst)); if (GET_MODE (src) == XOmode) - gcc_assert ((TARGET_DMF + gcc_assert ((TARGET_DENSE_MATH ? VSX_REGNO_P (REGNO (dst)) : FP_REGNO_P (REGNO (dst)))); if (GET_MODE (src) == OOmode) @@ -27472,9 +27474,9 @@ rs6000_split_multireg_move (rtx dst, rtx src) emit_insn (gen_rtx_SET (dst_i, op)); } - /* On systems without DMF where accumulators overlap with the vector - registers, we have to prime it after we've written it. */ - if (GET_MODE (src) == XOmode && !TARGET_DMF) + /* On systems without dense math where accumulators overlap with the + vector registers, we have to prime it after we've written it. */ + if (GET_MODE (src) == XOmode && !TARGET_DENSE_MATH) emit_insn (gen_mma_xxmtacc (dst, dst)); return; @@ -27485,9 +27487,9 @@ rs6000_split_multireg_move (rtx dst, rtx src) if (REG_P (src) && REG_P (dst) && (REGNO (src) < REGNO (dst))) { - /* If we are reading an accumulator register and we don't have DMF, we - have to deprime it before we can access it. */ - if (TARGET_MMA && !TARGET_DMF + /* If we are reading an accumulator register and we don't have dense + math, we have to deprime it before we can access it. */ + if (TARGET_MMA && !TARGET_DENSE_MATH && GET_MODE (src) == XOmode && FP_REGNO_P (REGNO (src))) emit_insn (gen_mma_xxmfacc (src, src)); @@ -27515,7 +27517,7 @@ rs6000_split_multireg_move (rtx dst, rtx src) /* If we are writing an accumulator register, we have to prime it after we've written it. */ - if (TARGET_MMA && !TARGET_DMF + if (TARGET_MMA && !TARGET_DENSE_MATH && GET_MODE (dst) == XOmode && FP_REGNO_P (REGNO (dst))) emit_insn (gen_mma_xxmtacc (dst, dst)); } @@ -27652,7 +27654,7 @@ rs6000_split_multireg_move (rtx dst, rtx src) /* If we are reading an accumulator register, we have to deprime it before we can access it. */ - if (TARGET_MMA && !TARGET_DMF && REG_P (src) + if (TARGET_MMA && !TARGET_DENSE_MATH && REG_P (src) && GET_MODE (src) == XOmode && FP_REGNO_P (REGNO (src))) emit_insn (gen_mma_xxmfacc (src, src)); @@ -27684,7 +27686,7 @@ rs6000_split_multireg_move (rtx dst, rtx src) /* If we are writing an accumulator register, we have to prime it after we've written it. */ - if (TARGET_MMA && !TARGET_DMF && REG_P (dst) + if (TARGET_MMA && !TARGET_DENSE_MATH && REG_P (dst) && GET_MODE (dst) == XOmode && FP_REGNO_P (REGNO (dst))) emit_insn (gen_mma_xxmtacc (dst, dst)); diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h index 640d8462ab8..5d38257ebff 100644 --- a/gcc/config/rs6000/rs6000.h +++ b/gcc/config/rs6000/rs6000.h @@ -662,7 +662,7 @@ extern unsigned char rs6000_recip_bits[]; #define UNITS_PER_FP_WORD 8 #define UNITS_PER_ALTIVEC_WORD 16 #define UNITS_PER_VSX_WORD 16 -#define UNITS_PER_DMF_WORD 128 +#define UNITS_PER_DMR_WORD 128 /* Type used for ptrdiff_t, as a string used in a declaration. */ #define PTRDIFF_TYPE "int" @@ -828,7 +828,7 @@ enum data_align { align_abi, align_opt, align_both }; 0, 0, 0, 0, 0, 0, 0, 0, \ /* vrsave vscr sfp */ \ 1, 1, 1, \ - /* DMF registers. */ \ + /* DMR registers. */ \ 0, 0, 0, 0, 0, 0, 0, 0 \ } @@ -854,7 +854,7 @@ enum data_align { align_abi, align_opt, align_both }; 1, 1, 0, 0, 0, 1, 1, 1, \ /* vrsave vscr sfp */ \ 0, 0, 0, \ - /* DMF registers. */ \ + /* DMR registers. */ \ 0, 0, 0, 0, 0, 0, 0, 0 \ } @@ -935,7 +935,7 @@ enum data_align { align_abi, align_opt, align_both }; 66, \ 83, 82, 81, 80, 79, 78, \ 95, 94, 93, 92, 91, 90, 89, 88, 87, 86, 85, 84, \ - /* DMF registers. */ \ + /* DMR registers. */ \ 111, 112, 113, 114, 115, 116, 117, 118, \ /* Vrsave, vscr, sfp. */ \ 108, 109, \ @@ -964,8 +964,8 @@ enum data_align { align_abi, align_opt, align_both }; /* True if register is a VSX register. */ #define VSX_REGNO_P(N) (FP_REGNO_P (N) || ALTIVEC_REGNO_P (N)) -/* True if register is a DMF register. */ -#define DMF_REGNO_P(N) ((N) >= FIRST_DMF_REGNO && (N) <= LAST_DMF_REGNO) +/* True if register is a DMR register. */ +#define DMR_REGNO_P(N) ((N) >= FIRST_DMR_REGNO && (N) <= LAST_DMR_REGNO) /* Alternate name for any vector register supporting floating point, no matter which instruction set(s) are available. */ @@ -1103,7 +1103,7 @@ enum reg_class FLOAT_REGS, ALTIVEC_REGS, VSX_REGS, - DMF_REGS, + DM_REGS, VRSAVE_REGS, VSCR_REGS, GEN_OR_FLOAT_REGS, @@ -1133,7 +1133,7 @@ enum reg_class "FLOAT_REGS", \ "ALTIVEC_REGS", \ "VSX_REGS", \ - "DMF_REGS", \ + "DM_REGS", \ "VRSAVE_REGS", \ "VSCR_REGS", \ "GEN_OR_FLOAT_REGS", \ @@ -1168,7 +1168,7 @@ enum reg_class { 0x00000000, 0x00000000, 0xffffffff, 0x00000000 }, \ /* VSX_REGS. */ \ { 0x00000000, 0xffffffff, 0xffffffff, 0x00000000 }, \ - /* DMF_REGS. */ \ + /* DM_REGS. */ \ { 0x00000000, 0x00000000, 0x00000000, 0x007f8000 }, \ /* VRSAVE_REGS. */ \ { 0x00000000, 0x00000000, 0x00000000, 0x00001000 }, \ diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index 242c4121157..8b1541c9b82 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -51,8 +51,8 @@ (VRSAVE_REGNO 108) (VSCR_REGNO 109) (FRAME_POINTER_REGNUM 110) - (FIRST_DMF_REGNO 111) - (LAST_DMF_REGNO 118) + (FIRST_DMR_REGNO 111) + (LAST_DMR_REGNO 118) ]) ;; @@ -356,7 +356,7 @@ (const (symbol_ref "(enum attr_cpu) rs6000_tune"))) ;; The ISA we implement. -(define_attr "isa" "any,p5,p6,p7,p7v,p8v,p9,p9v,p9kf,p9tf,p10,dmf,not_dmf" +(define_attr "isa" "any,p5,p6,p7,p7v,p8v,p9,p9v,p9kf,p9tf,p10,dm,not_dm" (const_string "any")) ;; Is this alternative enabled for the current CPU/ISA/etc.? @@ -405,12 +405,12 @@ (match_test "TARGET_POWER10")) (const_int 1) - (and (eq_attr "isa" "dmf") - (match_test "TARGET_DMF")) + (and (eq_attr "isa" "dm") + (match_test "TARGET_DENSE_MATH")) (const_int 1) - (and (eq_attr "isa" "not_dmf") - (match_test "!TARGET_DMF")) + (and (eq_attr "isa" "not_dm") + (match_test "!TARGET_DENSE_MATH")) (const_int 1) ] (const_int 0))) diff --git a/gcc/config/rs6000/rs6000.opt b/gcc/config/rs6000/rs6000.opt index b1d27ab9eb0..29a22ecc6b4 100644 --- a/gcc/config/rs6000/rs6000.opt +++ b/gcc/config/rs6000/rs6000.opt @@ -620,9 +620,9 @@ mieee128-constant Target Var(TARGET_IEEE128_CONSTANT) Init(1) Save Generate (do not generate) code that uses the LXVKQ instruction. -mdmf -Target Mask(DMF) Var(rs6000_isa_flags) -Generate (do not generate) DMF instructions. +mdense-math +Target Mask(DENSE_MATH) Var(rs6000_isa_flags) +Generate (do not generate) dense math instructions. mlagen Target Undocumented Mask(LAGEN) Var(rs6000_isa_flags)