From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1592) id D819B3858401; Tue, 1 Nov 2022 12:21:12 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org D819B3858401 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1667305272; bh=RU+4iVsYDTJKt7ox75UVFHokaJ7zuAAaurFfwvM4um0=; h=From:To:Subject:Date:From; b=YDDLr1bXbM42z1lBnJfBK03Cc1vtCPI/sFwLCV8bNl4P5igz+aGKfnCGOpewyAhJQ ICKEKsc/3FjP0uG5pycq6QD74FARjvP/8jTQHtaL58Yc/mIy/GPajV0dWsfxNih3Fg 8ChCTxVJmTYzFOVirNgzFtmLDnBH0vpBB9c3zMa0= MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="utf-8" From: Alexander Monakov To: gcc-cvs@gcc.gnu.org Subject: [gcc r13-3589] i386: correct integer division modeling in znver.md X-Act-Checkin: gcc X-Git-Author: Alexander Monakov X-Git-Refname: refs/heads/master X-Git-Oldrev: 0122faae30fe1ad1dfa8c69f3d3f0428b996b600 X-Git-Newrev: 5cee5f94000ee5eabce9b223c44c7923c1c69f61 Message-Id: <20221101122112.D819B3858401@sourceware.org> Date: Tue, 1 Nov 2022 12:21:12 +0000 (GMT) List-Id: https://gcc.gnu.org/g:5cee5f94000ee5eabce9b223c44c7923c1c69f61 commit r13-3589-g5cee5f94000ee5eabce9b223c44c7923c1c69f61 Author: Alexander Monakov Date: Mon Oct 31 17:35:57 2022 +0300 i386: correct integer division modeling in znver.md In znver.md, division instructions have descriptions like (define_insn_reservation "znver1_idiv_DI" 41 (and (eq_attr "cpu" "znver1,znver2") (and (eq_attr "type" "idiv") (and (eq_attr "mode" "DI") (eq_attr "memory" "none")))) "znver1-double,znver1-ieu2*41") which says that DImode idiv has latency 41 (which is correct) and that it occupies 2nd integer execution unit for 41 consecutive cycles, but that is not correct: 1) the division instruction is partially pipelined, and has throughput 1/14, not 1/41; 2) for the most part it occupies a separate division unit, not the general arithmetic unit. Evidently, interaction of such 41-cycle paths with the rest of reservations causes a combinatorial explosion in the automaton. Fix this by modeling the integer division unit properly, and correcting reservations to use the measured reciprocal throughput of those instructions (available from uops.info). A similar correction for floating-point divisions is left for a followup patch. Top 5 znver table sizes, before: 68692 r znver1_ieu_check 68692 r znver1_ieu_transitions 99792 r znver1_ieu_min_issue_delay 428108 r znver1_fp_min_issue_delay 856216 r znver1_fp_transitions After: 1454 r znver1_ieu_translate 1454 r znver1_translate 2304 r znver1_ieu_transitions 428108 r znver1_fp_min_issue_delay 856216 r znver1_fp_transitions gcc/ChangeLog: PR target/87832 * config/i386/znver.md (znver1_idiv): New automaton. (znver1-idiv): New unit. (znver1_idiv_DI): Correct unit and cycles in the reservation. (znver1_idiv_SI): Ditto. (znver1_idiv_HI): Ditto. (znver1_idiv_QI): Ditto. (znver1_idiv_mem_DI): Ditto. (znver1_idiv_mem_SI): Ditto. (znver1_idiv_mem_HI): Ditto. (znver1_idiv_mem_QI): Ditto. (znver3_idiv_DI): Ditto. (znver3_idiv_SI): Ditto. (znver3_idiv_HI): Ditto. (znver3_idiv_QI): Ditto. (znver3_idiv_mem_DI): Ditto. (znver3_idiv_mem_SI): Ditto. (znver3_idiv_mem_HI): Ditto. (znver3_idiv_mem_QI): Ditto. Diff: --- gcc/config/i386/znver.md | 39 +++++++++++++++++++++------------------ 1 file changed, 21 insertions(+), 18 deletions(-) diff --git a/gcc/config/i386/znver.md b/gcc/config/i386/znver.md index 9c25b4e27c3..4aa098fd80c 100644 --- a/gcc/config/i386/znver.md +++ b/gcc/config/i386/znver.md @@ -23,8 +23,8 @@ ;; AMD znver1, znver2 and znver3 Scheduling ;; Modeling automatons for zen decoders, integer execution pipes, -;; AGU pipes and floating point execution units. -(define_automaton "znver1, znver1_ieu, znver1_fp, znver1_agu") +;; SIMD/FP domain, AGU pipes, and dividers. +(define_automaton "znver1, znver1_ieu, znver1_fp, znver1_agu, znver1_idiv") ;; Decoders unit has 4 decoders and all of them can decode fast path ;; and vector type instructions. @@ -93,6 +93,9 @@ +znver1-fp2+znver1-fp3 +znver1-agu0+znver1-agu1+znver2-agu2") +;; Dividers +(define_cpu_unit "znver1-idiv" "znver1_idiv") + ;; Call instruction (define_insn_reservation "znver1_call" 1 (and (eq_attr "cpu" "znver1") @@ -176,28 +179,28 @@ (and (eq_attr "type" "idiv") (and (eq_attr "mode" "DI") (eq_attr "memory" "none")))) - "znver1-double,znver1-ieu2*41") + "znver1-double,znver1-idiv*14") (define_insn_reservation "znver1_idiv_SI" 25 (and (eq_attr "cpu" "znver1,znver2") (and (eq_attr "type" "idiv") (and (eq_attr "mode" "SI") (eq_attr "memory" "none")))) - "znver1-double,znver1-ieu2*25") + "znver1-double,znver1-idiv*14") (define_insn_reservation "znver1_idiv_HI" 17 (and (eq_attr "cpu" "znver1,znver2") (and (eq_attr "type" "idiv") (and (eq_attr "mode" "HI") (eq_attr "memory" "none")))) - "znver1-double,znver1-ieu2*17") + "znver1-double,znver1-idiv*14") (define_insn_reservation "znver1_idiv_QI" 12 (and (eq_attr "cpu" "znver1,znver2") (and (eq_attr "type" "idiv") (and (eq_attr "mode" "QI") (eq_attr "memory" "none")))) - "znver1-direct,znver1-ieu2*12") + "znver1-direct,znver1-idiv*13") ;; Mem operands (define_insn_reservation "znver1_idiv_mem_DI" 45 @@ -205,84 +208,84 @@ (and (eq_attr "type" "idiv") (and (eq_attr "mode" "DI") (eq_attr "memory" "none")))) - "znver1-double,znver1-load,znver1-ieu2*41") + "znver1-double,znver1-load,znver1-idiv*14") (define_insn_reservation "znver1_idiv_mem_SI" 29 (and (eq_attr "cpu" "znver1,znver2") (and (eq_attr "type" "idiv") (and (eq_attr "mode" "SI") (eq_attr "memory" "none")))) - "znver1-double,znver1-load,znver1-ieu2*25") + "znver1-double,znver1-load,znver1-idiv*14") (define_insn_reservation "znver1_idiv_mem_HI" 21 (and (eq_attr "cpu" "znver1,znver2") (and (eq_attr "type" "idiv") (and (eq_attr "mode" "HI") (eq_attr "memory" "none")))) - "znver1-double,znver1-load,znver1-ieu2*17") + "znver1-double,znver1-load,znver1-idiv*14") (define_insn_reservation "znver1_idiv_mem_QI" 16 (and (eq_attr "cpu" "znver1,znver2") (and (eq_attr "type" "idiv") (and (eq_attr "mode" "QI") (eq_attr "memory" "none")))) - "znver1-direct,znver1-load,znver1-ieu2*12") + "znver1-direct,znver1-load,znver1-idiv*13") (define_insn_reservation "znver3_idiv_DI" 18 (and (eq_attr "cpu" "znver3") (and (eq_attr "type" "idiv") (and (eq_attr "mode" "DI") (eq_attr "memory" "none")))) - "znver1-double,znver1-ieu2*18") + "znver1-double,znver1-idiv*7") (define_insn_reservation "znver3_idiv_SI" 12 (and (eq_attr "cpu" "znver3") (and (eq_attr "type" "idiv") (and (eq_attr "mode" "SI") (eq_attr "memory" "none")))) - "znver1-double,znver1-ieu2*12") + "znver1-double,znver1-idiv*6") (define_insn_reservation "znver3_idiv_HI" 10 (and (eq_attr "cpu" "znver3") (and (eq_attr "type" "idiv") (and (eq_attr "mode" "HI") (eq_attr "memory" "none")))) - "znver1-double,znver1-ieu2*10") + "znver1-double,znver1-idiv*4") (define_insn_reservation "znver3_idiv_QI" 9 (and (eq_attr "cpu" "znver3") (and (eq_attr "type" "idiv") (and (eq_attr "mode" "QI") (eq_attr "memory" "none")))) - "znver1-direct,znver1-ieu2*9") + "znver1-direct,znver1-idiv*4") (define_insn_reservation "znver3_idiv_mem_DI" 22 (and (eq_attr "cpu" "znver3") (and (eq_attr "type" "idiv") (and (eq_attr "mode" "DI") (eq_attr "memory" "load")))) - "znver1-double,znver1-load,znver1-ieu2*22") + "znver1-double,znver1-load,znver1-idiv*7") (define_insn_reservation "znver3_idiv_mem_SI" 16 (and (eq_attr "cpu" "znver3") (and (eq_attr "type" "idiv") (and (eq_attr "mode" "SI") (eq_attr "memory" "load")))) - "znver1-double,znver1-load,znver1-ieu2*16") + "znver1-double,znver1-load,znver1-idiv*6") (define_insn_reservation "znver3_idiv_mem_HI" 14 (and (eq_attr "cpu" "znver3") (and (eq_attr "type" "idiv") (and (eq_attr "mode" "HI") (eq_attr "memory" "load")))) - "znver1-double,znver1-load,znver1-ieu2*10") + "znver1-double,znver1-load,znver1-idiv*4") (define_insn_reservation "znver3_idiv_mem_QI" 13 (and (eq_attr "cpu" "znver3") (and (eq_attr "type" "idiv") (and (eq_attr "mode" "QI") (eq_attr "memory" "load")))) - "znver1-direct,znver1-load,znver1-ieu2*9") + "znver1-direct,znver1-load,znver1-idiv*4") ;; STR ISHIFT which are micro coded. ;; Fix me: Latency need to be rechecked.