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From: Michael Meissner <meissner@gcc.gnu.org>
To: gcc-cvs@gcc.gnu.org
Subject: [gcc(refs/users/meissner/heads/dmf003)] Revert patches.
Date: Sat, 5 Nov 2022 03:01:09 +0000 (GMT) [thread overview]
Message-ID: <20221105030109.5C1D93858C60@sourceware.org> (raw)
https://gcc.gnu.org/g:580e7ef412aa920b945e33bae418377e7b451712
commit 580e7ef412aa920b945e33bae418377e7b451712
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Fri Nov 4 23:00:56 2022 -0400
Revert patches.
Diff:
---
gcc/ChangeLog.meissner | 18 ++++++---
gcc/config/rs6000/mma.md | 98 ++++++------------------------------------------
2 files changed, 24 insertions(+), 92 deletions(-)
diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner
index bb8c5c1749e..d8f8c5ea6e6 100644
--- a/gcc/ChangeLog.meissner
+++ b/gcc/ChangeLog.meissner
@@ -1,3 +1,15 @@
+==================== Dmf003 branch, patch #15.
+
+Add dense math test.
+
+2022-11-04 Michael Meissner <meissner@linux.ibm.com>
+
+gcc/testsuite/
+
+ * gcc.target/powerpc/dm-double-test.c: New test.
+ * lib/target-supports.exp (check_effective_target_ppc_dmr_ok): New
+ target test.
+
==================== Dmf003 branch, patch #14.
Switch to dense math names for all MMA operations.
@@ -67,12 +79,6 @@ gcc/
(rs6000_split_multireg_move): Do not generate accumulator prime or
de-prime instructions if dense math.
-gcc/testsuite/
-
- * gcc.target/powerpc/dm-double-test.c: New test.
- * lib/target-supports.exp (check_effective_target_ppc_dmr_ok): New
- target test.
-
==================== Dmf003 branch, patch #12.
Add support for accumulators in DMR registers.
diff --git a/gcc/config/rs6000/mma.md b/gcc/config/rs6000/mma.md
index cca1fa71f75..835f34e8e00 100644
--- a/gcc/config/rs6000/mma.md
+++ b/gcc/config/rs6000/mma.md
@@ -227,22 +227,13 @@
(define_int_attr vvi4i4i8 [(UNSPEC_MMA_PMXVI4GER8 "pmxvi4ger8")])
-(define_int_attr vvi4i4i8_dm [(UNSPEC_MMA_PMXVI4GER8 "pmdmxvi4ger8")])
-
(define_int_attr avvi4i4i8 [(UNSPEC_MMA_PMXVI4GER8PP "pmxvi4ger8pp")])
-(define_int_attr avvi4i4i8_dm [(UNSPEC_MMA_PMXVI4GER8PP "pmdmxvi4ger8pp")])
-
(define_int_attr vvi4i4i2 [(UNSPEC_MMA_PMXVI16GER2 "pmxvi16ger2")
(UNSPEC_MMA_PMXVI16GER2S "pmxvi16ger2s")
(UNSPEC_MMA_PMXVF16GER2 "pmxvf16ger2")
(UNSPEC_MMA_PMXVBF16GER2 "pmxvbf16ger2")])
-(define_int_attr vvi4i4i2_dm [(UNSPEC_MMA_PMXVI16GER2 "pmdmxvi16ger2")
- (UNSPEC_MMA_PMXVI16GER2S "pmdmxvi16ger2s")
- (UNSPEC_MMA_PMXVF16GER2 "pmdmxvf16ger2")
- (UNSPEC_MMA_PMXVBF16GER2 "pmdmxvbf16ger2")])
-
(define_int_attr avvi4i4i2 [(UNSPEC_MMA_PMXVI16GER2PP "pmxvi16ger2pp")
(UNSPEC_MMA_PMXVI16GER2SPP "pmxvi16ger2spp")
(UNSPEC_MMA_PMXVF16GER2PP "pmxvf16ger2pp")
@@ -254,54 +245,25 @@
(UNSPEC_MMA_PMXVBF16GER2NP "pmxvbf16ger2np")
(UNSPEC_MMA_PMXVBF16GER2NN "pmxvbf16ger2nn")])
-(define_int_attr avvi4i4i2_dm [(UNSPEC_MMA_PMXVI16GER2PP "pmdmxvi16ger2pp")
- (UNSPEC_MMA_PMXVI16GER2SPP "pmdmxvi16ger2spp")
- (UNSPEC_MMA_PMXVF16GER2PP "pmdmxvf16ger2pp")
- (UNSPEC_MMA_PMXVF16GER2PN "pmdmxvf16ger2pn")
- (UNSPEC_MMA_PMXVF16GER2NP "pmdmxvf16ger2np")
- (UNSPEC_MMA_PMXVF16GER2NN "pmdmxvf16ger2nn")
- (UNSPEC_MMA_PMXVBF16GER2PP "pmdmxvbf16ger2pp")
- (UNSPEC_MMA_PMXVBF16GER2PN "pmdmxvbf16ger2pn")
- (UNSPEC_MMA_PMXVBF16GER2NP "pmdmxvbf16ger2np")
- (UNSPEC_MMA_PMXVBF16GER2NN "pmdmxvbf16ger2nn")])
-
(define_int_attr vvi4i4 [(UNSPEC_MMA_PMXVF32GER "pmxvf32ger")])
-(define_int_attr vvi4i4_dm [(UNSPEC_MMA_PMXVF32GER "pmdmxvf32ger")])
-
(define_int_attr avvi4i4 [(UNSPEC_MMA_PMXVF32GERPP "pmxvf32gerpp")
(UNSPEC_MMA_PMXVF32GERPN "pmxvf32gerpn")
(UNSPEC_MMA_PMXVF32GERNP "pmxvf32gernp")
(UNSPEC_MMA_PMXVF32GERNN "pmxvf32gernn")])
-(define_int_attr avvi4i4_dm [(UNSPEC_MMA_PMXVF32GERPP "pmdmxvf32gerpp")
- (UNSPEC_MMA_PMXVF32GERPN "pmdmxvf32gerpn")
- (UNSPEC_MMA_PMXVF32GERNP "pmdmxvf32gernp")
- (UNSPEC_MMA_PMXVF32GERNN "pmdmxvf32gernn")])
-
(define_int_attr pvi4i2 [(UNSPEC_MMA_PMXVF64GER "pmxvf64ger")])
-(define_int_attr pvi4i2_dm [(UNSPEC_MMA_PMXVF64GER "pmdmxvf64ger")])
-
(define_int_attr apvi4i2 [(UNSPEC_MMA_PMXVF64GERPP "pmxvf64gerpp")
(UNSPEC_MMA_PMXVF64GERPN "pmxvf64gerpn")
(UNSPEC_MMA_PMXVF64GERNP "pmxvf64gernp")
(UNSPEC_MMA_PMXVF64GERNN "pmxvf64gernn")])
-(define_int_attr apvi4i2_dm [(UNSPEC_MMA_PMXVF64GERPP "pmdmxvf64gerpp")
- (UNSPEC_MMA_PMXVF64GERPN "pmdmxvf64gerpn")
- (UNSPEC_MMA_PMXVF64GERNP "pmdmxvf64gernp")
- (UNSPEC_MMA_PMXVF64GERNN "pmdmxvf64gernn")])
-
(define_int_attr vvi4i4i4 [(UNSPEC_MMA_PMXVI8GER4 "pmxvi8ger4")])
-(define_int_attr vvi4i4i4_dm [(UNSPEC_MMA_PMXVI8GER4 "pmdmxvi8ger4")])
-
(define_int_attr avvi4i4i4 [(UNSPEC_MMA_PMXVI8GER4PP "pmxvi8ger4pp")
(UNSPEC_MMA_PMXVI8GER4SPP "pmxvi8ger4spp")])
-(define_int_attr avvi4i4i4_dm [(UNSPEC_MMA_PMXVI8GER4PP "pmdmxvi8ger4pp")
- (UNSPEC_MMA_PMXVI8GER4SPP "pmdmxvi8ger4spp")])
;; Vector pair support. OOmode can only live in VSRs.
(define_expand "movoo"
@@ -653,10 +615,7 @@
(match_operand:V16QI 2 "vsx_register_operand" "wa,v,?wa")]
MMA_VV))]
"TARGET_MMA"
- "@
- dm<vv> %A0,%x1,%x2
- <vv> %A0,%x1,%x2
- <vv> %A0,%x1,%x2"
+ "<vv> %A0,%x1,%x2"
[(set_attr "type" "mma")
(set_attr "isa" "dm,not_dm,not_dm")])
@@ -677,10 +636,7 @@
(match_operand:V16QI 2 "vsx_register_operand" "wa,v,?wa")]
MMA_PV))]
"TARGET_MMA"
- "@
- dm<pv> %A0,%x1,%x2
- <pv> %A0,%x1,%x2
- <pv> %A0,%x1,%x2"
+ "<pv> %A0,%x1,%x2"
[(set_attr "type" "mma")
(set_attr "isa" "dm,not_dm,not_dm")])
@@ -691,10 +647,7 @@
(match_operand:V16QI 3 "vsx_register_operand" "wa,v,?wa")]
MMA_APV))]
"TARGET_MMA"
- "@
- dm<apv> %A0,%x2,%x3
- <apv> %A0,%x2,%x3
- <apv> %A0,%x2,%x3"
+ "<apv> %A0,%x2,%x3"
[(set_attr "type" "mma")
(set_attr "isa" "dm,not_dm,not_dm")])
@@ -707,10 +660,7 @@
(match_operand:SI 5 "u8bit_cint_operand" "n,n,n")]
MMA_VVI4I4I8))]
"TARGET_MMA"
- "@
- dm<vvi4i4i8> %A0,%x1,%x2,%3,%4,%5
- <vvi4i4i8> %A0,%x1,%x2,%3,%4,%5
- <vvi4i4i8> %A0,%x1,%x2,%3,%4,%5"
+ "<vvi4i4i8> %A0,%x1,%x2,%3,%4,%5"
[(set_attr "type" "mma")
(set_attr "prefixed" "yes")
(set_attr "isa" "dm,not_dm,not_dm")])
@@ -739,10 +689,7 @@
(match_operand:SI 5 "const_0_to_3_operand" "n,n,n")]
MMA_VVI4I4I2))]
"TARGET_MMA"
- "@
- <vvi4i4i2_dm> %A0,%x1,%x2,%3,%4,%5
- <vvi4i4i2> %A0,%x1,%x2,%3,%4,%5
- <vvi4i4i2> %A0,%x1,%x2,%3,%4,%5"
+ "<vvi4i4i2> %A0,%x1,%x2,%3,%4,%5"
[(set_attr "type" "mma")
(set_attr "prefixed" "yes")
(set_attr "isa" "dm,not_dm,not_dm")])
@@ -757,10 +704,7 @@
(match_operand:SI 6 "const_0_to_3_operand" "n,n,n")]
MMA_AVVI4I4I2))]
"TARGET_MMA"
- "@
- <avvi4i4i2_dm> %A0,%x2,%x3,%4,%5,%6
- <avvi4i4i2> %A0,%x2,%x3,%4,%5,%6
- <avvi4i4i2> %A0,%x2,%x3,%4,%5,%6"
+ "<avvi4i4i2> %A0,%x2,%x3,%4,%5,%6"
[(set_attr "type" "mma")
(set_attr "prefixed" "yes")
(set_attr "isa" "dm,not_dm,not_dm")])
@@ -773,10 +717,7 @@
(match_operand:SI 4 "const_0_to_15_operand" "n,n,n")]
MMA_VVI4I4))]
"TARGET_MMA"
- "@
- <vvi4i4_dm> %A0,%x1,%x2,%3,%4
- <vvi4i4> %A0,%x1,%x2,%3,%4
- <vvi4i4> %A0,%x1,%x2,%3,%4"
+ "<vvi4i4> %A0,%x1,%x2,%3,%4"
[(set_attr "type" "mma")
(set_attr "prefixed" "yes")
(set_attr "isa" "dm,not_dm,not_dm")])
@@ -790,10 +731,7 @@
(match_operand:SI 5 "const_0_to_15_operand" "n,n,n")]
MMA_AVVI4I4))]
"TARGET_MMA"
- "@
- <avvi4i4_dm> %A0,%x2,%x3,%4,%5
- <avvi4i4> %A0,%x2,%x3,%4,%5
- <avvi4i4> %A0,%x2,%x3,%4,%5"
+ "<avvi4i4> %A0,%x2,%x3,%4,%5"
[(set_attr "type" "mma")
(set_attr "prefixed" "yes")
(set_attr "isa" "dm,not_dm,not_dm")])
@@ -806,10 +744,7 @@
(match_operand:SI 4 "const_0_to_3_operand" "n,n,n")]
MMA_PVI4I2))]
"TARGET_MMA"
- "@
- <pvi4i2_dm> %A0,%x1,%x2,%3,%4
- <pvi4i2> %A0,%x1,%x2,%3,%4
- <pvi4i2> %A0,%x1,%x2,%3,%4"
+ "<pvi4i2> %A0,%x1,%x2,%3,%4"
[(set_attr "type" "mma")
(set_attr "prefixed" "yes")
(set_attr "isa" "dm,not_dm,not_dm")])
@@ -823,10 +758,7 @@
(match_operand:SI 5 "const_0_to_3_operand" "n,n,n")]
MMA_APVI4I2))]
"TARGET_MMA"
- "@
- <apvi4i2_dm> %A0,%x2,%x3,%4,%5
- <apvi4i2> %A0,%x2,%x3,%4,%5
- <apvi4i2> %A0,%x2,%x3,%4,%5"
+ "<apvi4i2> %A0,%x2,%x3,%4,%5"
[(set_attr "type" "mma")
(set_attr "prefixed" "yes")
(set_attr "isa" "dm,not_dm,not_dm")])
@@ -840,10 +772,7 @@
(match_operand:SI 5 "const_0_to_15_operand" "n,n,n")]
MMA_VVI4I4I4))]
"TARGET_MMA"
- "@
- <vvi4i4i4_dm> %A0,%x1,%x2,%3,%4,%5
- <vvi4i4i4> %A0,%x1,%x2,%3,%4,%5
- <vvi4i4i4> %A0,%x1,%x2,%3,%4,%5"
+ "<vvi4i4i4> %A0,%x1,%x2,%3,%4,%5"
[(set_attr "type" "mma")
(set_attr "prefixed" "yes")
(set_attr "isa" "dm,not_dm,not_dm")])
@@ -858,10 +787,7 @@
(match_operand:SI 6 "const_0_to_15_operand" "n,n,n")]
MMA_AVVI4I4I4))]
"TARGET_MMA"
- "@
- <avvi4i4i4_dm> %A0,%x2,%x3,%4,%5,%6
- <avvi4i4i4> %A0,%x2,%x3,%4,%5,%6
- <avvi4i4i4> %A0,%x2,%x3,%4,%5,%6"
+ "<avvi4i4i4> %A0,%x2,%x3,%4,%5,%6"
[(set_attr "type" "mma")
(set_attr "prefixed" "yes")
(set_attr "isa" "dm,not_dm,not_dm")])
next reply other threads:[~2022-11-05 3:01 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-11-05 3:01 Michael Meissner [this message]
-- strict thread matches above, loose matches on Subject: below --
2022-11-05 3:23 Michael Meissner
2022-11-05 2:49 Michael Meissner
2022-11-04 19:19 Michael Meissner
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