From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1005) id 346233858283; Wed, 9 Nov 2022 05:58:26 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 346233858283 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1667973507; bh=hQB53t/JIkfB/5FMz31pu+8WINuhDKXF3RrIiCMrdHg=; h=From:To:Subject:Date:From; b=i733VDpBnrbgXKaZSq1MWIyNbQeur/o9LfS3p+sfWVo4EzhkQXByauL4PvmR3At6N vStdTmFyxgqvOTNDKu2Vy9XPftt9n+NK35lj38s3stMGZm4BJ36zYCTurC4NyOcAoO 90ia31617SxK8rS/uDdWCK7eaoEbH42n7BgKLox4= Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit From: Michael Meissner To: gcc-cvs@gcc.gnu.org Subject: [gcc(refs/users/meissner/heads/dmf004)] Update ChangeLog.meissner. X-Act-Checkin: gcc X-Git-Author: Michael Meissner X-Git-Refname: refs/users/meissner/heads/dmf004 X-Git-Oldrev: 066a6abfa5efb4611b5a3a907d55b01767baddd5 X-Git-Newrev: 539e5cf18d507b3a5b57a8597cfd8f6bc9985157 Message-Id: <20221109055827.346233858283@sourceware.org> Date: Wed, 9 Nov 2022 05:58:26 +0000 (GMT) List-Id: https://gcc.gnu.org/g:539e5cf18d507b3a5b57a8597cfd8f6bc9985157 commit 539e5cf18d507b3a5b57a8597cfd8f6bc9985157 Author: Michael Meissner Date: Wed Nov 9 00:58:09 2022 -0500 Update ChangeLog.meissner. 2022-11-09 Michael Meissner gcc/ * ChangeLog.meissner: Update. Diff: --- gcc/ChangeLog.meissner | 237 +++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 237 insertions(+) diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner index 5a6fa542ab6..0c43af20d62 100644 --- a/gcc/ChangeLog.meissner +++ b/gcc/ChangeLog.meissner @@ -1,3 +1,240 @@ +==================== Dmf004 branch, patch #15. + +Add support for 1,024 bit DMR registers. + +2022-11-09 Michael Meissner + +gcc/ + + * config/rs6000/mma.md (UNSPEC_DM_INSERT512_UPPER): New unspec. + (UNSPEC_DM_INSERT512_LOWER): Likewise. + (UNSPEC_DM_EXTRACT512): Likewise. + (UNSPEC_DMR_RELOAD_FROM_MEMORY): Likewise. + (UNSPEC_DMR_RELOAD_TO_MEMORY): Likewise. + (movtdo): New define_expand and define_insn_and_split to implement 1,024 + bit DMR registers. + (movtdo_insert512_upper): New insn. + (movtdo_insert512_lower): Likewise. + (movtdo_extract512): Likewise. + (reload_dmr_from_memory): Likewise. + (reload_dmr_to_memory): Likewise. + * config/rs6000/rs6000-builtin.cc (rs6000_type_string): Add DMR + support. + (rs6000_init_builtins): Add support for __dmr keyword. + * config/rs6000/rs6000-call.cc (rs6000_return_in_memory): Add support + for TDOmode. + (rs6000_function_arg): Likewise. + * config/rs6000/rs6000-modes.def (TDOmode): New mode. + * config/rs6000/rs6000.cc (rs6000_hard_regno_nregs_internal): Add + support for TDOmode. + (rs6000_hard_regno_mode_ok_uncached): Likewise. + (rs6000_hard_regno_mode_ok): Likewise. + (rs6000_modes_tieable_p): Likewise. + (rs6000_debug_reg_global): Likewise. + (rs6000_setup_reg_addr_masks): Likewise. + (rs6000_init_hard_regno_mode_ok): Add support for TDOmode. Setup reload + hooks for DMR mode. + (reg_offset_addressing_ok_p): Add support for TDOmode. + (rs6000_emit_move): Likewise. + (rs6000_secondary_reload_simple_move): Likewise. + (rs6000_secondary_reload_class): Likewise. + (rs6000_mangle_type): Add mangling for __dmr type. + (rs6000_dmr_register_move_cost): Add support for TDOmode. + (rs6000_split_multireg_move): Likewise. + (rs6000_invalid_conversion): Likewise. + * config/rs6000/rs6000.h (VECTOR_ALIGNMENT_P): Add TDOmode. + (enum rs6000_builtin_type_index): Add DMR type nodes. + (dmr_type_node): Likewise. + (ptr_dmr_type_node): Likewise. + +gcc/testsuite/ + + * gcc.target/powerpc/dm-1024bit.c: New test. + +==================== Dmf004 branch, patch #14. + +Switch to dense math names for all MMA operations. + +2022-11-04 Michael Meissner + +gcc/ + + * config/rs6000/mma.md (vvi4i4i8_dm): New int attribute. + (avvi4i4i8_dm): Likewise. + (vvi4i4i2_dm): Likewise. + (avvi4i4i2_dm): Likewise. + (vvi4i4_dm): Likewise. + (avvi4i4_dm): Likewise. + (pvi4i2_dm): Likewise. + (apvi4i2_dm): Likewise. + (vvi4i4i4_dm): Likewise. + (avvi4i4i4_dm): Likewise. + (mma_): Add support for running on DMF systems, generating the dense + math instruction and using the dense math accumulators. + (mma_): Likewise. + (mma_): Likewise. + (mma_): Likewise. + (mma_): Likewise. + (mma_): Likewise. + (mma_): Likewise. + (mma_): Likewise. + (mma_): Likewise. + (mma_): Likewise. + (mma_): Likewise. + (mma_): Likewise. + +gcc/testsuite/ + + * gcc.target/powerpc/dm-double-test.c: New test. + * lib/target-supports.exp (check_effective_target_ppc_dmr_ok): New + target test. + +==================== Dmf004 branch, patch #13. + +Make MMA insns support dmr registers. + +2022-11-09 Michael Meissner + +gcc/ + + * config/rs6000/mma.md (mma_): New define_expand to handle + mma_ for dense math and non dense math. + (mma_ insn): Restrict to non dense math. + (mma_xxsetaccz): Convert to define_expand to handle non dense math and + dense math. + (mma_xxsetaccz_p10): Rename from mma_xxsetaccz and restrict usage to non + dense math. + (mma_xxsetaccz_dm): Dense math version of mma_xxsetaccz. + (mma_): Add support for dense math. + (mma_): Likewise. + (mma_): Likewise. + (mma_): Likewise. + (mma_): Likewise. + (mma_): Likewise. + (mma_): Likewise. + (mma_): Likewise. + (mma_): Likewise. + (mma_): Likewise. + (mma_): Likewise. + (mma_): Likewise. + (mma_): Likewise. + (mma_): Likewise. + * config/rs6000/rs6000-c.cc (rs6000_target_modify_macros): Define + __PPC_DMR__ if we have dense math instructions. + * config/rs6000/rs6000.cc (print_operand): Make %A handle only DMRs if + dense math and only FPRs if not dense math. + (rs6000_split_multireg_move): Do not generate accumulator prime or + de-prime instructions if dense math. + +==================== Dmf004 branch, patch #12. + +Add support for accumulators in DMR registers. + +2022-11-09 Michael Meissner + +gcc/ + + * config/rs6000/constraints.md (wD constraint): New constraint. + * config/rs6000/mma.md (UNSPEC_DM_ASSEMBLE_ACC): New unspec. + (movxo): Convert into define_expand. + (movxo_fpr): Version of movxo where accumulators overlap with FPRs. + (movxo_dm): Dense math version of movxo. + (mma_assemble_acc): Add dense match support to define_expand. + (mma_assemble_acc_fpr): Rename from mma_assemble_acc, and restrict it to + non dense math. + (mma_assemble_acc_dm): Dense math version of mma_assemble_acc. + (mma_disassemble_acc): Add dense math support to define_expand. + (mma_disassemble_acc_fpr): Rename from mma_disassemble_acc, and restrict + it to non dense math. + (mma_disassemble_acc_dm): Dense math version of mma_disassemble_acc. + * config/rs6000/predicates.md (dmr_operand): New predicate. + (accumulator_operand): Likewise. + * config/rs6000/rs6000-cpus.def (ISA_FUTURE_MASKS): Add -mdense-math. + (POWERPC_MASKS): Likewise. + * config/rs6000/rs6000.cc (enum rs6000_reg_type): Add DMR_REG_TYPE. + (enum rs6000_reload_reg_type): Add RELOAD_REG_DMR. + (LAST_RELOAD_REG_CLASS): Add support for DMR registers. + (reload_reg_map): Likewise. + (rs6000_reg_names): Likewise. + (alt_reg_names): Likewise. + (rs6000_hard_regno_nregs_internal): Likewise. + (rs6000_hard_regno_mode_ok_uncached): Likewise. + (rs6000_debug_reg_global): Likewise. + (rs6000_setup_reg_addr_masks): Likewise. + (rs6000_init_hard_regno_mode_ok): Likewise. + (rs6000_option_override_internal): Add checking for -mdense-math. + (rs6000_secondary_reload_memory): Add support for DMR registers. + (rs6000_secondary_reload_simple_move): Likewise. + (rs6000_preferred_reload_class): Likewise. + (rs6000_secondary_reload_class): Likewise. + (print_operand): Make %A handle both FPRs and DMRs. + (rs6000_dmr_register_move_cost): New helper function. + (rs6000_register_move_cost): Add support for DMR registers. + (rs6000_memory_move_cost): Likewise. + (rs6000_compute_pressure_classes): Likewise. + (rs6000_debugger_regno): Likewise. + (rs6000_opt_masks): Add -mdense-math. + (rs6000_split_multireg_move): Add support for DMRs. + * config/rs6000/rs6000.h (UNITS_PER_DMR_WORD): New macro. + (FIRST_PSEUDO_REGISTER): Update for DMRs. + (FIXED_REGISTERS): Add DMRs. + (CALL_REALLY_USED_REGISTERS): Likewise. + (REG_ALLOC_ORDER): Likewise. + (enum reg_class): Add DM_REGS. + (REG_CLASS_NAMES): Likewise. + (REG_CLASS_CONTENTS): Likewise. + * config/rs6000/rs6000.md (FIRST_DMR_REGNO): New constant. + (LAST_DMR_REGNO): Likewise. + (isa attribute): Add 'dm' and 'not_dm' attributes. + (enabled attribute): Support 'dm' and 'not_dm' attributes. + * config/rs6000/rs6000.opt (-mdense-math): New switch. + * doc/md.texi (PowerPC constraints): Document wD constraint. + +==================== Dmf004 branch, patch #11. + +Make -mcpu=future enable -mblock-ops-vector-pair. + +2022-11-09 Michael Meissner + +gcc/ + + * config/rs6000/rs6000-cpus.def (ISA_FUTURE_MASKS): Add + -mblock-ops-vector-pair. + (POWERPC_MASKS): Likewise. + +==================== Dmf004 branch, patch #10. + +Add -mcpu=future. + +2022-11-09 Michael Meissner + +gcc/ + + * config/rs6000/rs6000-c.cc (rs6000_target_modify_macros): Define + __ARCH_PWR_FUTURE__ if -mcpu=future. + * config/rs6000/rs6000-cpus.def (ISA_FUTURE_MASKS): New macro. + (POWERPC_MASKS): Add -mfuture. + * config/rs6000/rs6000-opts.h (enum processor_type): Add + PROCESSOR_FUTURE. + * config/rs6000/rs6000-tables.opt: Regenerate. + * config/rs6000/rs6000.cc (rs6000_option_override_internal): Add + -mcpu=future support. Make -mtune=future act like -mtune=power10 for + now. + (rs6000_machine_from_flags): Likewise. + (rs6000_reassociation_width): Likewise. + (rs6000_adjust_cost): Likewise. + (rs6000_issue_rate): Likewise. + (rs6000_sched_reorder): Likewise. + (rs6000_sched_reorder2): Likewise. + (rs6000_register_move_cost): Likewise. + (rs6000_opt_masks): Add -mfuture. + * config/rs6000/rs6000.h (ASM_CPU_SUPPORT): Likewise. + * config/rs6000/rs6000.opt (-mfuture): New undocumented debug switch. + * config/rs6000/rs6000.md (cpu attribute): Add -mcpu=future support. + * doc/invoke.texi (IBM RS/6000 and PowerPC Options): Document -mcpu=future. + ==================== Dmf004 branch, patch #4. Patch libgcc to always use _Float128 and _Complex _Float128 on PowerPC.