From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1923) id 882DC3858D20; Thu, 10 Nov 2022 13:57:52 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 882DC3858D20 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1668088673; bh=08CEJBXRcX8hoU6ss/GebjbPuKSjUS0WdmvZ0xOzkFo=; h=From:To:Subject:Date:From; b=guufQRntQQFhH9XZi71UGt85R20W26zFc8K6Wf4I+pYlIumVo8DOFWOHjoA4gDMDm F0ur6vlpBThjuLT+MjRXPMkPQWKE7WJAd1bxKpnFb0TfLkzwe8SeQcIF5E0J1VwsK9 iARS0g/8ZVUInPSa7sxePklxMtBXekpYyJWhEOwk= MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="utf-8" From: Philipp Tomsich To: gcc-cvs@gcc.gnu.org Subject: [gcc r13-3878] RISC-V: Fix selection of pipeline model for sifive-7-series X-Act-Checkin: gcc X-Git-Author: Philipp Tomsich X-Git-Refname: refs/heads/master X-Git-Oldrev: 203b127fccc9abe5373c9e3cc03a476c35b1f594 X-Git-Newrev: 2f6cb9c51a933de19cd88f4c9180ac9cf5093522 Message-Id: <20221110135753.882DC3858D20@sourceware.org> Date: Thu, 10 Nov 2022 13:57:52 +0000 (GMT) List-Id: https://gcc.gnu.org/g:2f6cb9c51a933de19cd88f4c9180ac9cf5093522 commit r13-3878-g2f6cb9c51a933de19cd88f4c9180ac9cf5093522 Author: Philipp Tomsich Date: Thu Nov 10 00:43:05 2022 +0100 RISC-V: Fix selection of pipeline model for sifive-7-series A few of the gcc.target/riscv/mcpu-*.c tests have been failing for a while now, due to the pipeline model for sifive-7-series not being selected despite -mtune=sifive-7-series. The root cause is that the respective RISCV_TUNE entry points to generic instead. Fix this. Fixes 97d1ed67fc6 ("RISC-V: Support --target-help for -mcpu/-mtune") gcc/ChangeLog: * config/riscv/riscv-cores.def (RISCV_TUNE): Update sifive-7-series to point to the sifive_7 pipeline description. Diff: --- gcc/config/riscv/riscv-cores.def | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/gcc/config/riscv/riscv-cores.def b/gcc/config/riscv/riscv-cores.def index b84ad999ac1..31ad34682c5 100644 --- a/gcc/config/riscv/riscv-cores.def +++ b/gcc/config/riscv/riscv-cores.def @@ -36,7 +36,7 @@ RISCV_TUNE("rocket", generic, rocket_tune_info) RISCV_TUNE("sifive-3-series", generic, rocket_tune_info) RISCV_TUNE("sifive-5-series", generic, rocket_tune_info) -RISCV_TUNE("sifive-7-series", generic, sifive_7_tune_info) +RISCV_TUNE("sifive-7-series", sifive_7, sifive_7_tune_info) RISCV_TUNE("thead-c906", generic, thead_c906_tune_info) RISCV_TUNE("size", generic, optimize_size_tune_info)