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From: Jakub Jelinek <jakub@gcc.gnu.org> To: gcc-cvs@gcc.gnu.org Subject: [gcc r13-4048] libatomic: Handle AVX+CX16 AMD like Intel for 16b atomics [PR104688] Date: Tue, 15 Nov 2022 07:18:41 +0000 (GMT) [thread overview] Message-ID: <20221115071841.12ED9382E50E@sourceware.org> (raw) https://gcc.gnu.org/g:4a7a846687e076eae58ad3ea959245b2bf7fdc07 commit r13-4048-g4a7a846687e076eae58ad3ea959245b2bf7fdc07 Author: Jakub Jelinek <jakub@redhat.com> Date: Tue Nov 15 08:14:45 2022 +0100 libatomic: Handle AVX+CX16 AMD like Intel for 16b atomics [PR104688] We got a response from AMD in https://gcc.gnu.org/bugzilla/show_bug.cgi?id=104688#c10 so the following patch starts treating AMD with AVX and CMPXCHG16B ISAs like Intel by using vmovdqa for atomic load/store in libatomic. We still don't have confirmation from Zhaoxin and VIA (anything else with CPUs featuring AVX and CX16?). 2022-11-15 Jakub Jelinek <jakub@redhat.com> PR target/104688 * config/x86/init.c (__libat_feat1_init): Don't clear bit_AVX on AMD CPUs. Diff: --- libatomic/config/x86/init.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/libatomic/config/x86/init.c b/libatomic/config/x86/init.c index 6f6499c58c3..10e1c5f5dbb 100644 --- a/libatomic/config/x86/init.c +++ b/libatomic/config/x86/init.c @@ -39,10 +39,12 @@ __libat_feat1_init (void) == (bit_AVX | bit_CMPXCHG16B)) { /* Intel SDM guarantees that 16-byte VMOVDQA on 16-byte aligned address - is atomic, but so far we don't have this guarantee from AMD. */ + is atomic, and AMD is going to do something similar soon. + We don't have a guarantee from vendors of other CPUs with AVX, + like Zhaoxin and VIA. */ unsigned int ecx2 = 0; __get_cpuid (0, &eax, &ebx, &ecx2, &edx); - if (ecx2 != signature_INTEL_ecx) + if (ecx2 != signature_INTEL_ecx && ecx2 != signature_AMD_ecx) FEAT1_REGISTER &= ~bit_AVX; } #endif
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