From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1923) id 5AD703895FF2; Tue, 15 Nov 2022 14:00:27 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 5AD703895FF2 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1668520827; bh=T9Kd33utJOegz+XWpSTDBcHChSsrxO2gymfxEvU5+D4=; h=From:To:Subject:Date:From; b=Qg84Fal6/EOiGi+5cdMWU+y/Ukyo3ba+aMMcgc574s6KZRpe0IftQJ2JJwyQYJ4Kk qkzgyn0W5EGHy6NGTCrFrcycSYBX3ROf5O0q03ZFjH8mvOJNRwBDdsyyZOGx/V6Cqv XUj6qVxRW7qxhO7T7MnglPeaGxjqNDn6Lc6kfJH4= Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit From: Philipp Tomsich To: gcc-cvs@gcc.gnu.org Subject: [gcc(refs/vendors/vrull/heads/for-upstream)] RISC-V: split to allow formation of sh[123]add before 32bit divw X-Act-Checkin: gcc X-Git-Author: Philipp Tomsich X-Git-Refname: refs/vendors/vrull/heads/for-upstream X-Git-Oldrev: d67fd1ea93402c5ec736c141955173e8a3cee966 X-Git-Newrev: e322d16dbdfe2965b4310fa6bfdbcf7530a5a11e Message-Id: <20221115140027.5AD703895FF2@sourceware.org> Date: Tue, 15 Nov 2022 14:00:27 +0000 (GMT) List-Id: https://gcc.gnu.org/g:e322d16dbdfe2965b4310fa6bfdbcf7530a5a11e commit e322d16dbdfe2965b4310fa6bfdbcf7530a5a11e Author: Philipp Tomsich Date: Tue Nov 8 20:45:51 2022 +0100 RISC-V: split to allow formation of sh[123]add before 32bit divw When using strength-reduction, we will reduce a multiplication to a sequence of shifts and adds. If this is performed with 32-bit types and followed by a division, the lack of w-form sh[123]add will make combination impossible and lead to a slli + addw being generated. Split the sequence with the knowledge that a w-form div will perform implicit sign-extensions. gcc/ChangeLog: * config/riscv/bitmanip.md: Add a define_split to optimize slliw + addiw + divw into sh[123]add + divw. gcc/testsuite/ChangeLog: * gcc.target/riscv/zba-shNadd-05.c: New test. Signed-off-by: Philipp Tomsich Series-to: gcc-patches@gcc.gnu.org Series-cc: Palmer Dabbelt Series-cc: Vineet Gupta Series-cc: Christoph Muellner Series-cc: Kito Cheng Series-cc: Jeff Law Diff: --- gcc/config/riscv/bitmanip.md | 17 +++++++++++++++++ gcc/testsuite/gcc.target/riscv/zba-shNadd-05.c | 11 +++++++++++ 2 files changed, 28 insertions(+) diff --git a/gcc/config/riscv/bitmanip.md b/gcc/config/riscv/bitmanip.md index 1d603906cb2..75252c37df2 100644 --- a/gcc/config/riscv/bitmanip.md +++ b/gcc/config/riscv/bitmanip.md @@ -39,6 +39,23 @@ [(set_attr "type" "bitmanip") (set_attr "mode" "")]) +; When using strength-reduction, we will reduce a multiplication to a +; sequence of shifts and adds. If this is performed with 32-bit types +; and followed by a division, the lack of w-form sh[123]add will make +; combination impossible and lead to a slli + addw being generated. +; Split the sequence with the knowledge that a w-form div will perform +; implicit sign-extensions. +(define_split + [(set (match_operand:DI 0 "register_operand") + (sign_extend:DI (div:SI (plus:SI (subreg:SI (ashift:DI (match_operand:DI 1 "register_operand") + (match_operand:QI 2 "imm123_operand")) 0) + (subreg:SI (match_operand:DI 3 "register_operand") 0)) + (subreg:SI (match_operand:DI 4 "register_operand") 0)))) + (clobber (match_operand:DI 5 "register_operand"))] + "TARGET_64BIT && TARGET_ZBA" + [(set (match_dup 5) (plus:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3))) + (set (match_dup 0) (sign_extend:DI (div:SI (subreg:SI (match_dup 5) 0) (subreg:SI (match_dup 4) 0))))]) + (define_insn "*shNadduw" [(set (match_operand:DI 0 "register_operand" "=r") (plus:DI diff --git a/gcc/testsuite/gcc.target/riscv/zba-shNadd-05.c b/gcc/testsuite/gcc.target/riscv/zba-shNadd-05.c new file mode 100644 index 00000000000..271c3a8c0ac --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/zba-shNadd-05.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zba -mabi=lp64" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-O1" "-Os" "-Oz" "-Og" } } */ + +long long f(int a, int b) +{ + return (a * 3) / b; +} + +/* { dg-final { scan-assembler-times "sh1add\t" 1 } } */ +/* { dg-final { scan-assembler-times "divw\t" 1 } } */