From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1923) id 5D7823896C02; Tue, 15 Nov 2022 14:02:34 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 5D7823896C02 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1668520954; bh=5W3o6b98DRqG4XoFwRw1paDIgB72Dc99iAkukP7nzHg=; h=From:To:Subject:Date:From; b=uBSe9bDz28Om0VickP+dmcoB902I1Bc2cx4HQTB1SbKPw244n8JEeeJowLEchSHKO MsewAvlulzjTWdOTnjqVyJPQD3QzNjr4i1v5u89b+EL3yvpqcbxm+1wmA828xmNO/f 6V1rPLIMnJ8w9isUsumiPXsyA9XipU8ZpC9jYi8g= Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit From: Philipp Tomsich To: gcc-cvs@gcc.gnu.org Subject: [gcc(refs/vendors/vrull/heads/for-upstream)] RISC-V: Split "(a & (1UL << bitno)) ? 0 : -1" to bext + addi X-Act-Checkin: gcc X-Git-Author: Philipp Tomsich X-Git-Refname: refs/vendors/vrull/heads/for-upstream X-Git-Oldrev: 78df89a90553391570ebf96bcb89e250077aa396 X-Git-Newrev: c4af9ca07ccb5ae4085284a242d082fc4e7176d1 Message-Id: <20221115140234.5D7823896C02@sourceware.org> Date: Tue, 15 Nov 2022 14:02:34 +0000 (GMT) List-Id: https://gcc.gnu.org/g:c4af9ca07ccb5ae4085284a242d082fc4e7176d1 commit c4af9ca07ccb5ae4085284a242d082fc4e7176d1 Author: Philipp Tomsich Date: Wed May 11 13:50:11 2022 +0200 RISC-V: Split "(a & (1UL << bitno)) ? 0 : -1" to bext + addi For a straightforward application of bext for the following function long bext64(long a, char bitno) { return (a & (1UL << bitno)) ? 0 : -1; } we generate srl a0,a0,a1 # 7 [c=4 l=4] lshrdi3 andi a0,a0,1 # 8 [c=4 l=4] anddi3/1 addi a0,a0,-1 # 14 [c=4 l=4] adddi3/1 due to the following failed match at combine time: (set (reg:DI 82) (zero_extract:DI (reg:DI 83) (const_int 1 [0x1]) (reg:DI 84))) The existing pattern for bext requires the 3rd argument to zero_extract to be a QImode register wrapped in a zero_extension. This adds an additional pattern that allows an Xmode argument. With this change, the testcase compiles to bext a0,a0,a1 # 8 [c=4 l=4] *bextdi addi a0,a0,-1 # 14 [c=4 l=4] adddi3/1 gcc/ChangeLog: * config/riscv/bitmanip.md (*bext): Add an additional pattern that allows the 3rd argument to zero_extract to be an Xmode register operand. gcc/testsuite/ChangeLog: * gcc.target/riscv/zbs-bext.c: Add testcases. * gcc.target/riscv/zbs-bexti.c: Add testcases. Series-to: gcc-patches@gcc.gnu.org Series-cc: Kito Cheng Series-cc: Palmer Dabbelt Series-cc: Vineet Gupta Series-cc: Christoph Muellner Series-cc: Jeff Law Diff: --- gcc/config/riscv/bitmanip.md | 12 ++++++++++++ gcc/testsuite/gcc.target/riscv/zbs-bext.c | 23 ++++++++++++++++++++--- gcc/testsuite/gcc.target/riscv/zbs-bexti.c | 25 ++++++++++++++++++------- 3 files changed, 50 insertions(+), 10 deletions(-) diff --git a/gcc/config/riscv/bitmanip.md b/gcc/config/riscv/bitmanip.md index 06bf6b42dbd..a5170baceaf 100644 --- a/gcc/config/riscv/bitmanip.md +++ b/gcc/config/riscv/bitmanip.md @@ -652,6 +652,18 @@ "bext\t%0,%1,%2" [(set_attr "type" "bitmanip")]) +;; When performing `(a & (1UL << bitno)) ? 0 : -1` the combiner +;; usually has the `bitno` typed as X-mode (i.e. no further +;; zero-extension is performed around the bitno). +(define_insn "*bext" + [(set (match_operand:X 0 "register_operand" "=r") + (zero_extract:X (match_operand:X 1 "register_operand" "r") + (const_int 1) + (match_operand:X 2 "register_operand" "r")))] + "TARGET_ZBS" + "bext\t%0,%1,%2" + [(set_attr "type" "bitmanip")]) + (define_insn "*bexti" [(set (match_operand:X 0 "register_operand" "=r") (zero_extract:X (match_operand:X 1 "register_operand" "r") diff --git a/gcc/testsuite/gcc.target/riscv/zbs-bext.c b/gcc/testsuite/gcc.target/riscv/zbs-bext.c index 47982396119..8de9c5a167c 100644 --- a/gcc/testsuite/gcc.target/riscv/zbs-bext.c +++ b/gcc/testsuite/gcc.target/riscv/zbs-bext.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ /* { dg-options "-march=rv64gc_zbs -mabi=lp64" } */ -/* { dg-skip-if "" { *-*-* } { "-O0" } } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" } } */ /* bext */ long @@ -16,6 +16,23 @@ foo1 (long i) return 1L & (i >> 20); } +long bext64_1(long a, char bitno) +{ + return (a & (1UL << bitno)) ? 1 : 0; +} + +long bext64_2(long a, char bitno) +{ + return (a & (1UL << bitno)) ? 0 : -1; +} + +long bext64_3(long a, char bitno) +{ + return (a & (1UL << bitno)) ? -1 : 0; +} + /* { dg-final { scan-assembler-times "bexti\t" 1 } } */ -/* { dg-final { scan-assembler-times "bext\t" 1 } } */ -/* { dg-final { scan-assembler-not "andi" } } */ +/* { dg-final { scan-assembler-times "bext\t" 4 } } */ +/* { dg-final { scan-assembler-times "addi\t" 1 } } */ +/* { dg-final { scan-assembler-times "neg\t" 1 } } */ +/* { dg-final { scan-assembler-not "andi" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/riscv/zbs-bexti.c b/gcc/testsuite/gcc.target/riscv/zbs-bexti.c index 99e3b58309c..30b69c9bc3e 100644 --- a/gcc/testsuite/gcc.target/riscv/zbs-bexti.c +++ b/gcc/testsuite/gcc.target/riscv/zbs-bexti.c @@ -1,14 +1,25 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc_zbs -mabi=lp64 -O2" } */ +/* { dg-options "-march=rv64gc_zbs -mabi=lp64" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" } } */ /* bexti */ -#define BIT_NO 4 +#define BIT_NO 21 -long -foo0 (long a) +long bexti64_1(long a, char bitno) { - return (a & (1 << BIT_NO)) ? 0 : -1; + return (a & (1UL << BIT_NO)) ? 1 : 0; } -/* { dg-final { scan-assembler "bexti" } } */ -/* { dg-final { scan-assembler "addi" } } */ +long bexti64_2(long a, char bitno) +{ + return (a & (1UL << BIT_NO)) ? 0 : -1; +} + +long bexti64_3(long a, char bitno) +{ + return (a & (1UL << BIT_NO)) ? -1 : 0; +} + +/* { dg-final { scan-assembler-times "bexti\t" 3 } } */ +/* { dg-final { scan-assembler-times "addi\t" 1 } } */ +/* { dg-final { scan-assembler-times "neg\t" 1 } } */