From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1923) id 67DD53896C31; Tue, 15 Nov 2022 14:59:47 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 67DD53896C31 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1668524387; bh=qlg6orev1bgMx/RD9qZBd8r2rfdvhhKabNmlwEdQg/U=; h=From:To:Subject:Date:From; b=GdfTklq1KkkrPoqfWsnqjSXLrB6VIHBKRkK2IjIyJLxGamJQ+qg8q0zzI1+mTMK7B DC/2wRw2jVtaFN6ZuAMVdIbNlHSLSuTpmTKf8xTCjc8wl8fNJV5S9IiGzNYJCqVlbc NiGkmFgeBRL3DA9FO7XGPmPoHasnoq3HE/Y3wLKM= Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit From: Philipp Tomsich To: gcc-cvs@gcc.gnu.org Subject: [gcc/vrull/heads/for-upstream] (18 commits) riscv: Add support for strlen inline expansion X-Act-Checkin: gcc X-Git-Author: Philipp Tomsich X-Git-Refname: refs/vendors/vrull/heads/for-upstream X-Git-Oldrev: d97e9be78f7a21e17250a8e682f8f6a810c7d442 X-Git-Newrev: 50881951576a7e3e048bfb84eac5b47966cf349e Message-Id: <20221115145947.67DD53896C31@sourceware.org> Date: Tue, 15 Nov 2022 14:59:47 +0000 (GMT) List-Id: The branch 'vrull/heads/for-upstream' was updated to point to: 50881951576a... riscv: Add support for strlen inline expansion It previously pointed to: d97e9be78f7a... riscv: Add support for strlen inline expansion Diff: !!! WARNING: THE FOLLOWING COMMITS ARE NO LONGER ACCESSIBLE (LOST): ------------------------------------------------------------------- d97e9be... riscv: Add support for strlen inline expansion bc337d7... riscv: Use by-pieces to do overlapping accesses in block_mo 4232c46... riscv: Move riscv_block_move_loop to separate file 3bfdd3d... riscv: Enable overlap-by-pieces via tune param 8dbcea6... riscv: bitmanip/zbb: Add prefix/postfix and enable visiblit 63d9d0e... RISC-V: Handle "(a & twobits) == singlebit" in branches usi 0533c21... RISC-V: Split "(a & (1UL << bitno)) ? 0 : 1" to bext + xori c4af9ca... RISC-V: Split "(a & (1UL << bitno)) ? 0 : -1" to bext + add 78df89a... RISC-V: Zihintpause: add __builtin_riscv_pause af343f9... RISC-V: Use .p2align for code-alignment 373e07c... ifcvt: add if-conversion to conditional-zero instructions 8960ad4... RISC-V: Ventana-VT1 supports XVentanaCondOps a86a5f1... RISC-V: Support immediates in XVentanaCondOps ecd722d... RISC-V: Add instruction fusion (for ventana-vt1) 5e04c5a... RISC-V: Add basic support for the Ventana-VT1 core 790bdb1... RISC-V: Recognize bexti in negated if-conversion 3e36588... RISC-V: Recognize sign-extract + and cases for XVentanaCond 49cf3af... RISC-V: Support noce_try_store_flag_mask as vt.maskc Summary of changes (added commits): ----------------------------------- 5088195... riscv: Add support for strlen inline expansion a0a82c7... riscv: Use by-pieces to do overlapping accesses in block_mo bd76c16... riscv: Move riscv_block_move_loop to separate file 1ab285c... riscv: Enable overlap-by-pieces via tune param 1490405... riscv: bitmanip/zbb: Add prefix/postfix and enable visiblit b09a434... RISC-V: Handle "(a & twobits) == singlebit" in branches usi 0a90878... RISC-V: Split "(a & (1UL << bitno)) ? 0 : 1" to bext + xori 60e9ac0... RISC-V: Split "(a & (1UL << bitno)) ? 0 : -1" to bext + add 11a36c1... RISC-V: Zihintpause: add __builtin_riscv_pause 4c3df1e... RISC-V: Use .p2align for code-alignment 7ff40c1... ifcvt: add if-conversion to conditional-zero instructions 21cbb5b... RISC-V: Ventana-VT1 supports XVentanaCondOps eb94818... RISC-V: Support immediates in XVentanaCondOps a91f812... RISC-V: Add instruction fusion (for ventana-vt1) b984846... RISC-V: Add basic support for the Ventana-VT1 core 01fd2fc... RISC-V: Recognize bexti in negated if-conversion 442eed7... RISC-V: Recognize sign-extract + and cases for XVentanaCond b80d64e... RISC-V: Support noce_try_store_flag_mask as vt.maskc