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From: Philipp Tomsich <ptomsich@gcc.gnu.org> To: gcc-cvs@gcc.gnu.org Subject: [gcc(refs/vendors/vrull/heads/for-upstream)] RISC-V: Handle "(a & twobits) == singlebit" in branches using Zbs Date: Tue, 15 Nov 2022 15:00:53 +0000 (GMT) [thread overview] Message-ID: <20221115150053.5794C3896C3A@sourceware.org> (raw) https://gcc.gnu.org/g:b09a4343c4ba252ae2afc9abc4f5c48ffdaebf7a commit b09a4343c4ba252ae2afc9abc4f5c48ffdaebf7a Author: Philipp Tomsich <philipp.tomsich@vrull.eu> Date: Sun Oct 16 12:48:26 2022 +0200 RISC-V: Handle "(a & twobits) == singlebit" in branches using Zbs Use Zbs when generating a sequence for "if ((a & twobits) == singlebit) ..." that can be expressed as bexti + bexti + andn. gcc/ChangeLog: * config/riscv/bitmanip.md (*branch<X:mode>_mask_twobits_equals_singlebit): Handle "if ((a & T) == C)" using Zbs, when T has 2 bits set and C has one of these tow bits set. * config/riscv/predicates.md (const_twobits_operand): New predicate. gcc/testsuite/ChangeLog: * gcc.target/riscv/zbs-if_then_else-01.c: New test. Series-to: gcc-patches@gcc.gnu.org Series-cc: Kito Cheng <kito.cheng@gmail.com> Series-cc: Palmer Dabbelt <palmer@rivosinc.com> Series-cc: Vineet Gupta <vineetg@rivosinc.com> Series-cc: Christoph Muellner <christoph.muellner@vrull.eu> Series-cc: Jeff Law <jlaw@ventanamicro.com> Diff: --- gcc/config/riscv/bitmanip.md | 42 ++++++++++++++++++++++ gcc/config/riscv/predicates.md | 5 +++ .../gcc.target/riscv/zbs-if_then_else-01.c | 20 +++++++++++ 3 files changed, 67 insertions(+) diff --git a/gcc/config/riscv/bitmanip.md b/gcc/config/riscv/bitmanip.md index d639760e1e2d..ee980714a240 100644 --- a/gcc/config/riscv/bitmanip.md +++ b/gcc/config/riscv/bitmanip.md @@ -698,3 +698,45 @@ "TARGET_ZBS" [(set (match_dup 0) (zero_extract:X (match_dup 1) (const_int 1) (match_dup 2))) (set (match_dup 0) (xor:X (match_dup 0) (const_int 1)))]) + +;; IF_THEN_ELSE: test for 2 bits of opposite polarity +(define_insn_and_split "*branch<X:mode>_mask_twobits_equals_singlebit" + [(set (pc) + (if_then_else (match_operator 1 "equality_operator" + [(and:X (match_operand:X 2 "register_operand" "r") + (match_operand:X 3 "const_twobits_operand" "i")) + (match_operand:X 4 "single_bit_mask_operand" "i")]) + (label_ref (match_operand 0 "" "")) + (pc))) + (clobber (match_scratch:X 5 "=&r")) + (clobber (match_scratch:X 6 "=&r"))] + "TARGET_ZBS && TARGET_ZBB && !SMALL_OPERAND (INTVAL (operands[3]))" + "#" + "&& reload_completed" + [(set (match_dup 5) (zero_extract:X (match_dup 2) + (const_int 1) + (match_dup 8))) + (set (match_dup 6) (zero_extract:X (match_dup 2) + (const_int 1) + (match_dup 9))) + (set (match_dup 6) (and:X (not:X (match_dup 6)) (match_dup 5))) + (set (pc) (if_then_else (match_op_dup 1 [(match_dup 6) (const_int 0)]) + (label_ref (match_dup 0)) + (pc)))] +{ + unsigned HOST_WIDE_INT twobits_mask = UINTVAL (operands[3]); + unsigned HOST_WIDE_INT singlebit_mask = UINTVAL (operands[4]); + + /* Make sure that the reference value has one of the bits of the mask set */ + if ((twobits_mask & singlebit_mask) == 0) + FAIL; + + int setbit = ctz_hwi (singlebit_mask); + int clearbit = ctz_hwi (twobits_mask & ~singlebit_mask); + + operands[1] = gen_rtx_fmt_ee (GET_CODE (operands[1]) == NE ? EQ : NE, + <X:MODE>mode, operands[6], GEN_INT(0)); + + operands[8] = GEN_INT (setbit); + operands[9] = GEN_INT (clearbit); +}) diff --git a/gcc/config/riscv/predicates.md b/gcc/config/riscv/predicates.md index 490bff688a77..6e34829a59bb 100644 --- a/gcc/config/riscv/predicates.md +++ b/gcc/config/riscv/predicates.md @@ -321,6 +321,11 @@ (and (match_code "const_int") (match_test "popcount_hwi (~UINTVAL (op)) == 2"))) +;; A CONST_INT operand that has exactly two bits set. +(define_predicate "const_twobits_operand" + (and (match_code "const_int") + (match_test "popcount_hwi (UINTVAL (op)) == 2"))) + ;; A CONST_INT operand that fits into the unsigned half of a ;; signed-immediate after the top bit has been cleared. (define_predicate "uimm_extra_bit_operand" diff --git a/gcc/testsuite/gcc.target/riscv/zbs-if_then_else-01.c b/gcc/testsuite/gcc.target/riscv/zbs-if_then_else-01.c new file mode 100644 index 000000000000..d249a841ff9c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/zbs-if_then_else-01.c @@ -0,0 +1,20 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zbb_zbs -mabi=lp64" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-O1" } } */ + +void g(); + +void f1 (long a) +{ + if ((a & ((1ul << 33) | (1 << 4))) == (1ul << 33)) + g(); +} + +void f2 (long a) +{ + if ((a & 0x12) == 0x10) + g(); +} + +/* { dg-final { scan-assembler-times "bexti\t" 2 } } */ +/* { dg-final { scan-assembler-times "andn\t" 1 } } */
next reply other threads:[~2022-11-15 15:00 UTC|newest] Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top 2022-11-15 15:00 Philipp Tomsich [this message] -- strict thread matches above, loose matches on Subject: below -- 2022-11-18 11:35 Philipp Tomsich 2022-11-15 14:02 Philipp Tomsich
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