From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1005) id DA828395C05E; Wed, 16 Nov 2022 18:54:44 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org DA828395C05E DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1668624884; bh=mtaHastu5nqCxaLkWBW/PaVIKh5pkc9kuXPsGSQOP80=; h=From:To:Subject:Date:From; b=ng7y9pyWF5tSoDQGvgavJ0gByuySm+RWbS0/AIIR3DZrkGQJ0qJaxANObKtI787f/ R/okQXXGpIdV+sW+CVLGEulFJ2iGnmO6eF8yanAfjAlbFLuSakYYyYHY5GBG2qhLfu BdF2Ka6bhFY8gJhV31bnL6PfEBWLrqqblXfyQ13c= Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit From: Michael Meissner To: gcc-cvs@gcc.gnu.org Subject: [gcc(refs/users/meissner/heads/dmf004)] Add lxvprl and stxvprl support. X-Act-Checkin: gcc X-Git-Author: Michael Meissner X-Git-Refname: refs/users/meissner/heads/dmf004 X-Git-Oldrev: b530e25d13ec2cd1691d1f13b10a1fdbf9adf60b X-Git-Newrev: f7b34e9b400b925cf9860f65498b04bb5f66db22 Message-Id: <20221116185444.DA828395C05E@sourceware.org> Date: Wed, 16 Nov 2022 18:54:44 +0000 (GMT) List-Id: https://gcc.gnu.org/g:f7b34e9b400b925cf9860f65498b04bb5f66db22 commit f7b34e9b400b925cf9860f65498b04bb5f66db22 Author: Michael Meissner Date: Wed Nov 16 13:53:40 2022 -0500 Add lxvprl and stxvprl support. 2022-11-16 Michael Meissner gcc/ * config/rs6000/rs6000-string.cc (expand_block_move_variable): Add check for vect_partial_vector_usage before optimizing variable memcpys. Add support for lxvprl and stxvprl if we have them. * config/rs6000/rs6000.cc (rs6000_option_override_internal): Bump up memcpy inline size if we have lxvprl and stxvprl. * config/rs6000/vsx.md (lxvprl): New insn. (stxprl): New insn. Diff: --- gcc/config/rs6000/rs6000-string.cc | 27 +++++++++++++++++++-------- gcc/config/rs6000/rs6000.cc | 6 ++++++ gcc/config/rs6000/vsx.md | 23 +++++++++++++++++++++++ 3 files changed, 48 insertions(+), 8 deletions(-) diff --git a/gcc/config/rs6000/rs6000-string.cc b/gcc/config/rs6000/rs6000-string.cc index d14ee1da289..bc44d27773b 100644 --- a/gcc/config/rs6000/rs6000-string.cc +++ b/gcc/config/rs6000/rs6000-string.cc @@ -2752,6 +2752,7 @@ expand_block_move_variable (rtx operands[], bool might_overlap) || !TARGET_P9_VECTOR || !TARGET_64BIT || rs6000_memcpy_inline_bytes == 0 + || !param_vect_partial_vector_usage || might_overlap || !optimize || optimize_size) @@ -2765,10 +2766,11 @@ expand_block_move_variable (rtx operands[], bool might_overlap) ? copy_to_reg (operands[2]) : convert_to_mode (Pmode, operands[2], true)); - HOST_WIDE_INT var_size_int - = (rs6000_memcpy_inline_bytes > GET_MODE_SIZE (V16QImode) - ? GET_MODE_SIZE (V16QImode) - : rs6000_memcpy_inline_bytes); + int var_size_int + = (TARGET_FUTURE ? GET_MODE_SIZE (XOmode) : GET_MODE_SIZE (V16QImode)); + + if (var_size_int > rs6000_memcpy_inline_bytes) + var_size_int = rs6000_memcpy_inline_bytes; rtx var_size = GEN_INT (var_size_int); rtx var_cr = gen_reg_rtx (CCUNSmode); @@ -2794,10 +2796,19 @@ expand_block_move_variable (rtx operands[], bool might_overlap) emit_label (var_label); - /* We want to move bytes inline. Move 0..16 bytes now. */ - rtx vreg = gen_reg_rtx (V16QImode); - emit_insn (gen_lxvl (vreg, src_addr, bytes_rtx)); - emit_insn (gen_stxvl (vreg, dest_addr, bytes_rtx)); + /* We want to move bytes inline. Move 0..16 or 0..32 bytes now. */ + if (var_size_int > GET_MODE_SIZE (V16QImode)) + { + rtx vreg = gen_reg_rtx (XOmode); + emit_insn (gen_lxvprl (vreg, src_addr, bytes_rtx)); + emit_insn (gen_stxvprl (vreg, dest_addr, bytes_rtx)); + } + else + { + rtx vreg = gen_reg_rtx (V16QImode); + emit_insn (gen_lxvl (vreg, src_addr, bytes_rtx)); + emit_insn (gen_stxvl (vreg, dest_addr, bytes_rtx)); + } emit_label (join_label); return 1; diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc index dba37df3c61..e401aa4c02b 100644 --- a/gcc/config/rs6000/rs6000.cc +++ b/gcc/config/rs6000/rs6000.cc @@ -4878,6 +4878,12 @@ rs6000_option_override_internal (bool global_init_p) SET_OPTION_IF_UNSET (&global_options, &global_options_set, param_vect_partial_vector_usage, 0); + /* If we have the lxvprl/stxvprl instructions, bump up the default size + for doing inlining memcpy moves. */ + if (TARGET_FUTURE) + SET_OPTION_IF_UNSET (&global_options, &global_options_set, + rs6000_memcpy_inline_bytes, 32); + /* Use the 'model' -fsched-pressure algorithm by default. */ SET_OPTION_IF_UNSET (&global_options, &global_options_set, param_sched_pressure_algorithm, diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md index e4e73db9bb8..dfe61ae83e8 100644 --- a/gcc/config/rs6000/vsx.md +++ b/gcc/config/rs6000/vsx.md @@ -5804,6 +5804,29 @@ DONE; }) +;; There are no lxvpl and stxvpl instructions, so we can simplify the support +;; for lxvprl and stxvprl by not incorporating the shift left by 56 bits. +(define_insn "lxvprl" + [(set (match_operand:XO 0 "vsx_register_operand" "=wa") + (unspec:XO + [(match_operand:DI 1 "gpc_reg_operand" "b") + (mem:XO (match_dup 1)) + (match_operand:DI 2 "register_operand" "r")] + UNSPEC_LXVL))] + "TARGET_FUTURE && TARGET_64BIT" + "lxvprl %x0,%1,%2" + [(set_attr "type" "vecload")]) + +(define_insn "stxvprl" + [(set (mem:XO (match_operand:DI 1 "gpc_reg_operand" "b")) + (unspec:XO [(match_operand:XO 0 "vsx_register_operand" "wa") + (mem:XO (match_dup 1)) + (match_operand:DI 2 "register_operand" "r")] + UNSPEC_STXVLL))] + "TARGET_FUTURE" + "stxvprl %x0,%1,%2" + [(set_attr "type" "vecstore")]) + ;; Vector Compare Not Equal Byte (specified/not+eq:) (define_insn "vcmpneb" [(set (match_operand:V16QI 0 "altivec_register_operand" "=v")