[gcc r13-4123] middle-end: ensure that VEC_PERM operands get lowered to the same SSA_NAME. [PR107717]

[Tamar Christina <tnfchris@gcc.gnu.org>]

https://gcc.gnu.org/g:cbe313060cdcf1d857d42a9e16a1a03e5ff89fff

commit r13-4123-gcbe313060cdcf1d857d42a9e16a1a03e5ff89fff
Author: Tamar Christina <tamar.christina@arm.com>
Date:   Thu Nov 17 08:20:59 2022 +0000

    middle-end: ensure that VEC_PERM operands get lowered to the same SSA_NAME. [PR107717]
    
    At the moment when the VEC_PERMs generated by this match.pd rule is generated
    it creates two different SSA_NAMEs for the folded operand.  Because of this it
    the permute switches from a single operand permute to a two operand permute and
    the target may no longer support a permute for this.
    
    This fixes it by ensuring we generate the same SSA_NAME for both operands.
    
    gcc/ChangeLog:
    
            PR tree-optimization/107717
            * match.pd: Ensure same SSA_NAME.
    
    gcc/testsuite/ChangeLog:
    
            PR tree-optimization/107717
            * gcc.target/aarch64/sve2/pr107717.c: New test.

Diff:
---
 gcc/match.pd                                     | 4 ++--
 gcc/testsuite/gcc.target/aarch64/sve2/pr107717.c | 8 ++++++++
 2 files changed, 10 insertions(+), 2 deletions(-)

diff --git a/gcc/match.pd b/gcc/match.pd
index fe1178cf0d5..5aba1653b80 100644
--- a/gcc/match.pd
+++ b/gcc/match.pd
@@ -8262,7 +8262,7 @@ and,
  (simplify
   (op (vec_perm @0 @0 @2) (vec_perm @1 @1 @2))
    (if (VECTOR_INTEGER_TYPE_P (type))
-    (vec_perm (op @0 @1) (op @0 @1) @2))))
+    (vec_perm (op@3 @0 @1) @3 @2))))
 
 /* Similar for float arithmetic when permutation constant covers
    all vector elements.  */
@@ -8301,4 +8301,4 @@ and,
 	 }
       }
       (if (full_perm_p)
-	(vec_perm (op @0 @1) (op @0 @1) @2))))))
+	(vec_perm (op@3 @0 @1) @3 @2))))))
diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/pr107717.c b/gcc/testsuite/gcc.target/aarch64/sve2/pr107717.c
new file mode 100644
index 00000000000..09dc9afa61f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/sve2/pr107717.c
@@ -0,0 +1,8 @@
+/* { dg-do compile } */
+/* { dg-additional-options "-O3 -march=armv8-a+sve2" } */
+
+void foo(int n, char *restrict out, char *restrict in) {
+  for (int i=n; i-->0; ) {
+    out[i] += in[i];
+  }
+}