From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1005) id BD2B4384F6C6; Thu, 17 Nov 2022 21:54:04 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org BD2B4384F6C6 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1668722044; bh=AMKuEqVzhmKkK0LZ/HwcICu7/w6ApRBa2AlKvSkDod4=; h=From:To:Subject:Date:From; b=dvl00SNSCGK68LL4Is20wjOyC3XnrEH4yu/B0MV1HY8rYxfYsTohJ8uNYT5o9K8wO fr6u6MQNBcbrP5IurdLp9Wdhcmjzaga3Z2tvPJFPEhe+eH6a9RFvU39qW6nu7Nf78Z jEywJ38maFcqwdKlcvEaMy9o/G7SAxFsSfMEarOE= Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit From: Michael Meissner To: gcc-cvs@gcc.gnu.org Subject: [gcc(refs/users/meissner/heads/dmf004)] Update ChangeLog.meissner. X-Act-Checkin: gcc X-Git-Author: Michael Meissner X-Git-Refname: refs/users/meissner/heads/dmf004 X-Git-Oldrev: d1b721a25223e438195e18ac2db2e6f58bbd2a66 X-Git-Newrev: 7c6a0007d3c4a1764647cf35019c1541d5b9c36d Message-Id: <20221117215404.BD2B4384F6C6@sourceware.org> Date: Thu, 17 Nov 2022 21:54:04 +0000 (GMT) List-Id: https://gcc.gnu.org/g:7c6a0007d3c4a1764647cf35019c1541d5b9c36d commit 7c6a0007d3c4a1764647cf35019c1541d5b9c36d Author: Michael Meissner Date: Fri Nov 11 22:48:59 2022 -0500 Update ChangeLog.meissner. 2022-11-11 Michael Meissner gcc/ * ChangeLog.meissner: Update. Diff: --- gcc/ChangeLog.meissner | 39 +++++++++++++++++++++++++++++++++++++-- 1 file changed, 37 insertions(+), 2 deletions(-) diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner index c910d1b5625..3fa2264624b 100644 --- a/gcc/ChangeLog.meissner +++ b/gcc/ChangeLog.meissner @@ -1,6 +1,40 @@ +==================== Dmf004 branch, patch #17. + +Support load/store vector with right length. + +This patch adds support for new instructions that may be added to the PowerPC +architecture in the future to enhance the load and store vector with length +instructions. + +The current instructions (lxvl, lxvll, stxvl, and stxvll) are inconvient to use +since the count for the number of bytes must be in the top 8 bits of the GPR +register, instead of the bottom 8 bits. This meant that code generating these +instructions typically had to do a shift left by 56 bits to get the count into +the right position. In a future version of the PowerPC architecture, new +variants of these instructions might be added that expect the count to be in +the bottom 8 bits of the GPR register. These patches add this support to GCC +if the user uses the -mcpu=future option. + +2022-11-11 Michael Meissner + +gcc/ + + * config/rs6000/vsx.md (lxvl): If -mcpu=future, generate the lxvl with + the shift count automaticaly used in the insn. + (lxvrl): New insn for -mcpu=future. + (lxvrll): Likewise. + (stxvl): If -mcpu=future, generate the stxvl with the shift count + automaticaly used in the insn. + (stxvrl): New insn for -mcpu=future. + (stxvrll): Likewise. + +gcc/testsuite/ + + * gcc.target/powerpc/lxvrl.c: New test. + ==================== Dmf004 branch, patch #16. -Add saturating subtract built-in. +Add saturating subtract built-ins. This patch adds support for a saturating subtract built-in function that may be added to a future PowerPC processor. Note, if it is added, the name of the @@ -32,12 +66,13 @@ gcc/ built-in insn declarations. (sat_sub3_dot): Likewise. (sat_sub3_dot2): Likewise. + * doc/extend.texi (Future PowerPC built-ins): New section. gcc/testsuite/ * gcc.target/powerpc/subfus-1.c: New test. * gcc.target/powerpc/subfus-2.c: Likewise. - * lib/target-supports.exp (check_effective_target_powerpc_subfus_ok): + * lib/target-supports.exp (check_effective_target_powerpc_future_ok): New effective target. ==================== Dmf004 branch, patch #15.