[gcc(refs/vendors/vrull/heads/for-upstream)] RISC-V: allow bseti on SImode without sign-extension

[Philipp Tomsich <ptomsich@gcc.gnu.org>]

https://gcc.gnu.org/g:508091e2f93360bf1e143f0054779bd06871502d

commit 508091e2f93360bf1e143f0054779bd06871502d
Author: Philipp Tomsich <philipp.tomsich@vrull.eu>
Date:   Mon Oct 10 22:24:02 2022 +0200

    RISC-V: allow bseti on SImode without sign-extension
    
    As long as the SImode operand is not a partial subreg, we can use a
    bseti without postprocessing to or in a bit, as the middle end is
    smart enough to stay away from the signbit.
    
    gcc/ChangeLog:
    
            * config/riscv/bitmanip.md (*bsetidisi): New pattern.
    
    gcc/testsuite/ChangeLog:
    
            * gcc.target/riscv/zbs-bexti-02.c: New test.
    
    Series-to: gcc-patches@gcc.gnu.org
    Series-cc: Palmer Dabbelt <palmer@rivosinc.com>
    Series-cc: Vineet Gupta <vineetg@rivosinc.com>
    Series-cc: Christoph Muellner <christoph.muellner@vrull.eu>
    Series-cc: Kito Cheng <kito.cheng@gmail.com>
    Series-cc: Jeff Law <jlaw@ventanamicro.com>

Diff:
---
 gcc/config/riscv/bitmanip.md                  | 12 ++++++++++++
 gcc/testsuite/gcc.target/riscv/zbs-bseti-02.c | 25 +++++++++++++++++++++++++
 2 files changed, 37 insertions(+)

diff --git a/gcc/config/riscv/bitmanip.md b/gcc/config/riscv/bitmanip.md
index cd1e00ba6c2..2f89fd6aee1 100644
--- a/gcc/config/riscv/bitmanip.md
+++ b/gcc/config/riscv/bitmanip.md
@@ -416,6 +416,18 @@
   "bseti\t%0,%1,%S2"
   [(set_attr "type" "bitmanip")])
 
+;; As long as the SImode operand is not a partial subreg, we can use a
+;; bseti without postprocessing, as the middle end is smart enough to
+;; stay away from the signbit.
+(define_insn "*bsetidisi"
+  [(set (match_operand:DI 0 "register_operand" "=r")
+	(ior:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "r"))
+		(match_operand 2 "single_bit_mask_operand" "i")))]
+  "TARGET_ZBS && TARGET_64BIT
+   && !partial_subreg_p (operands[2])"
+  "bseti\t%0,%1,%S2"
+  [(set_attr "type" "bitmanip")])
+
 (define_insn "*bclr<mode>"
   [(set (match_operand:X 0 "register_operand" "=r")
 	(and:X (rotate:X (const_int -2)
diff --git a/gcc/testsuite/gcc.target/riscv/zbs-bseti-02.c b/gcc/testsuite/gcc.target/riscv/zbs-bseti-02.c
new file mode 100644
index 00000000000..d3629946375
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/zbs-bseti-02.c
@@ -0,0 +1,25 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_zbs -mabi=lp64" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" } } */
+
+/* bexti */
+int f(int* a, int b)
+{
+  return ((*a << b) | (1 << 14));
+}
+
+int g(int a, int b)
+{
+  return ((a + b)| (1 << 30));
+}
+
+int h(int a, int b)
+{
+  return ((a + b)| (1ULL << 33));
+}
+
+/* { dg-final { scan-assembler-times "addw\t" 2 } } */
+/* { dg-final { scan-assembler-times "sllw\t" 1 } } */
+/* { dg-final { scan-assembler-times "bseti\t" 2 } } */
+/* { dg-final { scan-assembler-not "sext.w\t" } } */
+