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From: Philipp Tomsich <ptomsich@gcc.gnu.org> To: gcc-cvs@gcc.gnu.org Subject: [gcc(refs/vendors/vrull/heads/for-upstream)] RISC-V: Use binvi to cover more immediates than with xori alone Date: Thu, 17 Nov 2022 22:25:49 +0000 (GMT) [thread overview] Message-ID: <20221117222549.3CAD43854568@sourceware.org> (raw) https://gcc.gnu.org/g:289fd1a0b22bdcd5641711d3c662abd176a62d38 commit 289fd1a0b22bdcd5641711d3c662abd176a62d38 Author: Philipp Tomsich <philipp.tomsich@vrull.eu> Date: Tue Oct 11 23:43:45 2022 +0200 RISC-V: Use binvi to cover more immediates than with xori alone Sequences of the form "a ^ C" with C being the positive half of a signed immediate's range with one extra bit set in addtion are mapped to xori and one binvi to avoid using a temporary (and a multi-insn sequence to load C into that temporary). Commit-notes: - Depends on a predicate posted in "RISC-V: Optimize branches testing a bit-range or a shifted immediate". Depending on the order of applying these, I'll take care to pull that part out of the other patch if needed. END gcc/ChangeLog: * config/riscv/bitmanip.md (*binvi<mode>_extrabit): New pattern. gcc/testsuite/ChangeLog: * gcc.target/riscv/zbs-binvi.c: New test. Series-to: gcc-patches@gcc.gnu.org Series-cc: Palmer Dabbelt <palmer@rivosinc.com> Series-cc: Vineet Gupta <vineetg@rivosinc.com> Series-cc: Christoph Muellner <christoph.muellner@vrull.eu> Series-cc: Kito Cheng <kito.cheng@gmail.com> Series-cc: Jeff Law <jlaw@ventanamicro.com> Diff: --- gcc/config/riscv/bitmanip.md | 19 +++++++++++++++++++ gcc/testsuite/gcc.target/riscv/zbs-binvi.c | 22 ++++++++++++++++++++++ 2 files changed, 41 insertions(+) diff --git a/gcc/config/riscv/bitmanip.md b/gcc/config/riscv/bitmanip.md index d76ed54dff2..a06b381f42a 100644 --- a/gcc/config/riscv/bitmanip.md +++ b/gcc/config/riscv/bitmanip.md @@ -623,6 +623,25 @@ "binvi\t%0,%1,%S2" [(set_attr "type" "bitmanip")]) +; Catch those cases where we can use a binvi + xori or binvi + binvi +; instead of a lui + addi + xor sequence. +(define_insn_and_split "*binvi<mode>_extrabit" + [(set (match_operand:X 0 "register_operand" "=r") + (xor:X (match_operand:X 1 "register_operand" "r") + (match_operand:X 2 "uimm_extra_bit_operand" "i")))] + "TARGET_ZBS" + "#" + "&& reload_completed" + [(set (match_dup 0) (xor:X (match_dup 1) (match_dup 3))) + (set (match_dup 0) (xor:X (match_dup 0) (match_dup 4)))] +{ + unsigned HOST_WIDE_INT bits = UINTVAL (operands[2]); + unsigned HOST_WIDE_INT topbit = HOST_WIDE_INT_1U << floor_log2 (bits); + + operands[3] = GEN_INT (bits &~ topbit); + operands[4] = GEN_INT (topbit); +}) + (define_insn "*bext<mode>" [(set (match_operand:X 0 "register_operand" "=r") (zero_extract:X (match_operand:X 1 "register_operand" "r") diff --git a/gcc/testsuite/gcc.target/riscv/zbs-binvi.c b/gcc/testsuite/gcc.target/riscv/zbs-binvi.c new file mode 100644 index 00000000000..c2d6725b53b --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/zbs-binvi.c @@ -0,0 +1,22 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zbs -mabi=lp64" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" } } */ + +long long f3(long long a) +{ + return a ^ 0x1100; +} + +long long f4 (long long a) +{ + return a ^ 0x80000000000000ffull; +} + +long long f5 (long long a) +{ + return a ^ 0x8000001000000000ull; +} + +/* { dg-final { scan-assembler-times "binvi\t" 4 } } */ +/* { dg-final { scan-assembler-times "xori\t" 2 } } */ +
next reply other threads:[~2022-11-17 22:25 UTC|newest] Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top 2022-11-17 22:25 Philipp Tomsich [this message] -- strict thread matches above, loose matches on Subject: below -- 2022-11-15 14:01 Philipp Tomsich
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