[gcc(refs/vendors/vrull/heads/for-upstream)] RISC-V: Recognize sign-extract + and cases for XVentanaCondOps

[Philipp Tomsich <ptomsich@gcc.gnu.org>]

https://gcc.gnu.org/g:f1cb12c4b880008d0de554384f68c4833bc74289

commit f1cb12c4b880008d0de554384f68c4833bc74289
Author: Philipp Tomsich <philipp.tomsich@vrull.eu>
Date:   Thu Mar 24 20:55:17 2022 +0100

    RISC-V: Recognize sign-extract + and cases for XVentanaCondOps
    
    Users might use explicit arithmetic operations to create a mask and
    then and it, in a sequence like
        cond = (bits >> SHIFT) & 1;
        mask = ~(cond - 1);
        val &= mask;
    which will present as a single-bit sign-extract.
    
    Dependening on what combination of XVentanaCondOps and Zbs are
    available, this will map to the following sequences:
     - bexti + vt.maskc, if both Zbs and XVentanaCondOps are present
     - andi + vt.maskc, if only XVentanaCondOps is available and the
                        sign-extract is operating on bits 10:0 (bit
                        11 can't be reached, as the immediate is
                        sign-extended)
     - slli + srli + and, otherwise.
    
    gcc/ChangeLog:
    
            * config/riscv/xventanacondops.md: Recognize SIGN_EXTRACT
              of a single-bit followed by AND for XVentanaCondOps.

Diff:
---
 gcc/config/riscv/xventanacondops.md                | 45 ++++++++++++++++++++++
 .../gcc.target/riscv/xventanacondops-le-01.c       |  2 +-
 2 files changed, 46 insertions(+), 1 deletion(-)

diff --git a/gcc/config/riscv/xventanacondops.md b/gcc/config/riscv/xventanacondops.md
index 3d7427519b3..f2eb886659f 100644
--- a/gcc/config/riscv/xventanacondops.md
+++ b/gcc/config/riscv/xventanacondops.md
@@ -78,3 +78,48 @@
   operands[6] = gen_rtx_fmt_ee (GET_CODE (operands[1]) == LE ? GT : GTU,
 				<X:MODE>mode, operands[2], operands[3]);
 })
+
+;; Users might use explicit arithmetic operations to create a mask and
+;; then and it, in a sequence like
+;;    cond = (bits >> SHIFT) & 1;
+;;    mask = ~(cond - 1);
+;;    val &= mask;
+;; which will present as a single-bit sign-extract in the combiner.
+;;
+;; This will give rise to any of the following cases:
+;; - with Zbs and XVentanaCondOps: bexti + vt.maskc
+;; - with XVentanaCondOps (but w/o Zbs):
+;;   - andi + vt.maskc, if the mask is representable in the immediate
+;;                      (which requires extra care due to the immediate
+;;                       being sign-extended)
+;;   - slli + srli + and
+;; - otherwise: slli + srli + and
+
+;; With Zbb, we have bexti for all possible bits...
+(define_split
+  [(set (match_operand:X 0 "register_operand")
+	(and:X (sign_extract:X (match_operand:X 1 "register_operand")
+			       (const_int 1)
+			       (match_operand 2 "immediate_operand"))
+	       (match_operand:X 3 "register_operand")))
+   (clobber (match_operand:X 4 "register_operand"))]
+  "TARGET_XVENTANACONDOPS && TARGET_ZBS"
+  [(set (match_dup 4) (zero_extract:X (match_dup 1) (const_int 1) (match_dup 2)))
+   (set (match_dup 0) (and:X (neg:X (ne:X (match_dup 4) (const_int 0)))
+			     (match_dup 3)))])
+
+;; ...whereas RV64I only allows us access to bits 0..10 in a single andi.
+(define_split
+  [(set (match_operand:X 0 "register_operand")
+	(and:X (sign_extract:X (match_operand:X 1 "register_operand")
+			       (const_int 1)
+			       (match_operand 2 "immediate_operand"))
+	       (match_operand:X 3 "register_operand")))
+   (clobber (match_operand:X 4 "register_operand"))]
+  "TARGET_XVENTANACONDOPS && !TARGET_ZBS && (UINTVAL (operands[2]) < 11)"
+  [(set (match_dup 4) (and:X (match_dup 1) (match_dup 2)))
+   (set (match_dup 0) (and:X (neg:X (ne:X (match_dup 4) (const_int 0)))
+			     (match_dup 3)))]
+{
+  operands[2] = GEN_INT(1 << UINTVAL(operands[2]));
+})
diff --git a/gcc/testsuite/gcc.target/riscv/xventanacondops-le-01.c b/gcc/testsuite/gcc.target/riscv/xventanacondops-le-01.c
index f6f80958e9d..eb463e3c161 100644
--- a/gcc/testsuite/gcc.target/riscv/xventanacondops-le-01.c
+++ b/gcc/testsuite/gcc.target/riscv/xventanacondops-le-01.c
@@ -4,7 +4,7 @@
 
 long long sink (long long);
 
-long long lt3 (long long a, long long b)
+long long le1 (long long a, long long b)
 {
   if (a <= b)
     b = 0;