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From: Philipp Tomsich <ptomsich@gcc.gnu.org> To: gcc-cvs@gcc.gnu.org Subject: [gcc/vrull/heads/for-upstream] (40 commits) riscv: Add support for strlen inline expansion Date: Fri, 18 Nov 2022 11:33:57 +0000 (GMT) [thread overview] Message-ID: <20221118113357.E637B384F6EA@sourceware.org> (raw) The branch 'vrull/heads/for-upstream' was updated to point to: 700a8672cef... riscv: Add support for strlen inline expansion It previously pointed to: 4c96c29290b... riscv: Add support for strlen inline expansion Diff: !!! WARNING: THE FOLLOWING COMMITS ARE NO LONGER ACCESSIBLE (LOST): ------------------------------------------------------------------- 4c96c29... riscv: Add support for strlen inline expansion f206e3f... riscv: Use by-pieces to do overlapping accesses in block_mo 7c3c415... riscv: Move riscv_block_move_loop to separate file 8071a7d... riscv: Enable overlap-by-pieces via tune param c0034ca... riscv: bitmanip/zbb: Add prefix/postfix and enable visiblit b988c88... RISC-V: Use .p2align for code-alignment 742a2b5... ifcvt: add if-conversion to conditional-zero instructions 84199cd... RISC-V: Ventana-VT1 supports XVentanaCondOps ccbf6d5... RISC-V: Support immediates in XVentanaCondOps 1908015... RISC-V: Add instruction fusion (for ventana-vt1) 84b7d1c... RISC-V: Add basic support for the Ventana-VT1 core fcf4728... RISC-V: Recognize bexti in negated if-conversion f1cb12c... RISC-V: Recognize sign-extract + and cases for XVentanaCond 966af83... RISC-V: Support noce_try_store_flag_mask as vt.maskc<n> 8187af4... RISC-V: Generate vt.maskc<n> on noce_try_store_flag_mask if 830289f... RISC-V: Recognize xventanacondops extension 5fdf1e0... RISC-V: Optimize masking with two clear bits not a SMALL_OP 289fd1a... RISC-V: Use binvi to cover more immediates than with xori a d99eeca... RISC-V: Use bseti to cover more immediates than with ori al 156bbf9... RISC-V: Replace zero_extendsidi2_shifted with generalized s 0598016... ifcombine: fold two bit tests with different polarity 8b07e62... ifcombine: recognize single bit test of sign-bit ac8c73c... RISC-V: Implement movmisalign<mode> to enable SLP 4aeab04... RISC-V: Optimise adding a (larger than simm12) constant to 19d866f... RISC-V: No extensions for SImode min/max against safe const e3560b1... RISC-V: Optimize branches testing a bit-range or a shifted 508091e... RISC-V: allow bseti on SImode without sign-extension e6aa763... RISC-V: Optimize slli(.uw)? + addw + zext.w into sh[123]add eed5fa2... RISC-V: split to allow formation of sh[123]add before 32bit 920c4e2... RISC-V: branch-(not)equals-zero compares against $zero Summary of changes (added commits): ----------------------------------- 700a867... riscv: Add support for strlen inline expansion 7481d2c... riscv: Use by-pieces to do overlapping accesses in block_mo 9c50c4e... riscv: Move riscv_block_move_loop to separate file 5b68949... riscv: Enable overlap-by-pieces via tune param 00cd924... riscv: bitmanip/zbb: Add prefix/postfix and enable visiblit 7bd124d... RISC-V: Use .p2align for code-alignment 8182811... ifcvt: add if-conversion to conditional-zero instructions 1b64c20... RISC-V: Ventana-VT1 supports XVentanaCondOps 4d26578... RISC-V: Support immediates in XVentanaCondOps efc6969... RISC-V: Add instruction fusion (for ventana-vt1) b228f85... RISC-V: Add basic support for the Ventana-VT1 core 7ee9e75... RISC-V: Recognize bexti in negated if-conversion 92ef983... RISC-V: Recognize sign-extract + and cases for XVentanaCond 1368fa4... RISC-V: Support noce_try_store_flag_mask as vt.maskc<n> 9422ef4... RISC-V: Generate vt.maskc<n> on noce_try_store_flag_mask if ea64d45... RISC-V: Recognize xventanacondops extension 4f1ddbe... RISC-V: Handle "(a & twobits) == singlebit" in branches usi a4558d1... RISC-V: Use bseti/bclri/binvi to extend reach of ori/andi/x 81c0dc3... RISC-V: Replace zero_extendsidi2_shifted with generalized s f525996... ifcombine: fold two bit tests with different polarity 1a9164c... ifcombine: recognize single bit test of sign-bit 34865c7... RISC-V: Implement movmisalign<mode> to enable SLP 32dcd20... RISC-V: Optimise adding a (larger than simm12) constant to a34c0e9... RISC-V: No extensions for SImode min/max against safe const 110d704... RISC-V: Optimize branches testing a bit-range or a shifted c71897e... RISC-V: allow bseti on SImode without sign-extension 26071b5... RISC-V: Optimize slli(.uw)? + addw + zext.w into sh[123]add e378300... RISC-V: split to allow formation of sh[123]add before 32bit d0a7eb7... RISC-V: branch-(not)equals-zero compares against $zero 20d2a8c... testsuite: Verify that module-mapper is available (*) 33de7b3... aarch64: Fix up LDAPR codegen (*) e5049df... c++: Implement CWG2635 - Constrained structured bindings (*) c5df839... tree-optimization/107647 - avoid FMA from SLP with -ffp-con (*) f0024bf... LoongArch: Fix atomic_exchange expanding [PR107713] (*) 7b3b2f5... c++: constinit on pointer to function [PR104066] (*) 3f467ea... c: Set the locus of the function result decl (*) 19be89d... Fortran: Remove double spaces in open() warning [PR99884] (*) ee89283... Fix PR 107734: valgrind errors with sbitmap in match.pd (*) 4e30622... [PR tree-optimization/107732] [range-ops] Handle attempt to (*) f9ed1d2... c, analyzer: fix ICE with -fanalyzer and -Wunused-macros [P (*) (*) This commit already exists in another branch. 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