From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1923) id 31788384D99E; Fri, 18 Nov 2022 11:34:18 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 31788384D99E DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1668771258; bh=62z2QfjI6BvWjYPcKjqKZHv5VPjoYNmZtJhn//pwX4I=; h=From:To:Subject:Date:From; b=UeY9MviZ97Hm7VwLuxzuUd6G9sQ/2epMsZ+3Z6z6CvXj7lTxySnhpPPJ5754d95qZ PTQNQvyctXw6/4TTCoTut3OWDKi57E1OxytnnDsaYzWWq7U0OOEP4YcLqVmO4G0/a9 1H33hN21qlDt20ORzD7/SakmRCIOie0YCBcZv+A8= Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit From: Philipp Tomsich To: gcc-cvs@gcc.gnu.org Subject: [gcc(refs/vendors/vrull/heads/for-upstream)] RISC-V: allow bseti on SImode without sign-extension X-Act-Checkin: gcc X-Git-Author: Philipp Tomsich X-Git-Refname: refs/vendors/vrull/heads/for-upstream X-Git-Oldrev: 26071b5acbea5e1ba40cb153bcb890f5512ea120 X-Git-Newrev: c71897ea6f9cb3d9827f4807a0647f38460fb202 Message-Id: <20221118113418.31788384D99E@sourceware.org> Date: Fri, 18 Nov 2022 11:34:18 +0000 (GMT) List-Id: https://gcc.gnu.org/g:c71897ea6f9cb3d9827f4807a0647f38460fb202 commit c71897ea6f9cb3d9827f4807a0647f38460fb202 Author: Philipp Tomsich Date: Mon Oct 10 22:24:02 2022 +0200 RISC-V: allow bseti on SImode without sign-extension As long as the SImode operand is not a partial subreg, we can use a bseti without postprocessing to or in a bit, as the middle end is smart enough to stay away from the signbit. gcc/ChangeLog: * config/riscv/bitmanip.md (*bsetidisi): New pattern. gcc/testsuite/ChangeLog: * gcc.target/riscv/zbs-bexti-02.c: New test. Series-to: gcc-patches@gcc.gnu.org Series-cc: Palmer Dabbelt Series-cc: Vineet Gupta Series-cc: Christoph Muellner Series-cc: Kito Cheng Series-cc: Jeff Law Diff: --- gcc/config/riscv/bitmanip.md | 12 ++++++++++++ gcc/testsuite/gcc.target/riscv/zbs-bseti-02.c | 25 +++++++++++++++++++++++++ 2 files changed, 37 insertions(+) diff --git a/gcc/config/riscv/bitmanip.md b/gcc/config/riscv/bitmanip.md index cd1e00ba6c2..2f89fd6aee1 100644 --- a/gcc/config/riscv/bitmanip.md +++ b/gcc/config/riscv/bitmanip.md @@ -416,6 +416,18 @@ "bseti\t%0,%1,%S2" [(set_attr "type" "bitmanip")]) +;; As long as the SImode operand is not a partial subreg, we can use a +;; bseti without postprocessing, as the middle end is smart enough to +;; stay away from the signbit. +(define_insn "*bsetidisi" + [(set (match_operand:DI 0 "register_operand" "=r") + (ior:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "r")) + (match_operand 2 "single_bit_mask_operand" "i")))] + "TARGET_ZBS && TARGET_64BIT + && !partial_subreg_p (operands[2])" + "bseti\t%0,%1,%S2" + [(set_attr "type" "bitmanip")]) + (define_insn "*bclr" [(set (match_operand:X 0 "register_operand" "=r") (and:X (rotate:X (const_int -2) diff --git a/gcc/testsuite/gcc.target/riscv/zbs-bseti-02.c b/gcc/testsuite/gcc.target/riscv/zbs-bseti-02.c new file mode 100644 index 00000000000..d3629946375 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/zbs-bseti-02.c @@ -0,0 +1,25 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zbs -mabi=lp64" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" } } */ + +/* bexti */ +int f(int* a, int b) +{ + return ((*a << b) | (1 << 14)); +} + +int g(int a, int b) +{ + return ((a + b)| (1 << 30)); +} + +int h(int a, int b) +{ + return ((a + b)| (1ULL << 33)); +} + +/* { dg-final { scan-assembler-times "addw\t" 2 } } */ +/* { dg-final { scan-assembler-times "sllw\t" 1 } } */ +/* { dg-final { scan-assembler-times "bseti\t" 2 } } */ +/* { dg-final { scan-assembler-not "sext.w\t" } } */ +