[gcc(refs/vendors/vrull/heads/for-upstream)] RISC-V: Recognize bexti in negated if-conversion

[Philipp Tomsich <ptomsich@gcc.gnu.org>]

https://gcc.gnu.org/g:7ee9e758ae0389a4b29b6cba6355bed682b835d2

commit 7ee9e758ae0389a4b29b6cba6355bed682b835d2
Author: Philipp Tomsich <philipp.tomsich@vrull.eu>
Date:   Wed Mar 30 00:01:30 2022 +0200

    RISC-V: Recognize bexti in negated if-conversion
    
    While the positive case "if ((bits >> SHAMT) & 1)" for SHAMT 0..10 can
    trigger conversion into efficient branchless sequences
      - with Zbs (bexti + neg + and)
      - with XVentanaCondOps (andi + vt.maskc)
    the inverted/negated case results in
      andi a5,a0,1024
      seqz a5,a5
      neg a5,a5
      and a5,a5,a1
    due to how the sequence presents to the combine pass.
    
    This adds an additional splitter to reassociate the polarity reversed
    case into bexti + addi, if Zbs is present.
    
    gcc/ChangeLog:
    
        * config/riscv/xventanacondops.md: Add split to reassociate
          "andi + seqz + neg" into "bexti + addi".
    
    Commit-changes: 2
    - Removed spurious empty line at the end of xventanacondops.md.

Diff:
---
 gcc/config/riscv/xventanacondops.md | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/gcc/config/riscv/xventanacondops.md b/gcc/config/riscv/xventanacondops.md
index f2eb886659f..1e01fe1c6de 100644
--- a/gcc/config/riscv/xventanacondops.md
+++ b/gcc/config/riscv/xventanacondops.md
@@ -123,3 +123,13 @@
 {
   operands[2] = GEN_INT(1 << UINTVAL(operands[2]));
 })
+
+(define_split
+  [(set (match_operand:X 0 "register_operand")
+	(neg:X (eq:X (zero_extract:X (match_operand:X 1 "register_operand")
+				     (const_int 1)
+				     (match_operand 2 "immediate_operand"))
+		     (const_int 0))))]
+  "!TARGET_XVENTANACONDOPS && TARGET_ZBS"
+  [(set (match_dup 0) (zero_extract:X (match_dup 1) (const_int 1) (match_dup 2)))
+   (set (match_dup 0) (plus:X (match_dup 0) (const_int -1)))])