From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1923) id 207DF3854562; Fri, 18 Nov 2022 20:22:02 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 207DF3854562 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1668802922; bh=YWxHHxfG4CccttQqGPvUYz1wI2cFv92uq/+MRzH486A=; h=From:To:Subject:Date:From; b=Z2luCsVMzG/vLFSZ1tL/vqqx3p20D7tdQK7ARca1iSjnrohUCk7UA3j7AMfLE5XfY ew6iY42x1vr2A2uweWXkRNAj45I/a/urmJMuWyvS4UYyYWn+FHUTgmlGN8yr/qPeSv ImOwzIGbxGXmlCmnxl1juE0u0BKxOJYVLr6L4E2w= Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit From: Philipp Tomsich To: gcc-cvs@gcc.gnu.org Subject: [gcc/vrull/heads/for-upstream] (38 commits) riscv: Add support for strlen inline expansion X-Act-Checkin: gcc X-Git-Author: Philipp Tomsich X-Git-Refname: refs/vendors/vrull/heads/for-upstream X-Git-Oldrev: 700a8672cef67a5ced0e091c39e61eec79b899e0 X-Git-Newrev: 1b1c78c31579bef64dfa44c459db2cd1eca4926c Message-Id: <20221118202202.207DF3854562@sourceware.org> Date: Fri, 18 Nov 2022 20:22:02 +0000 (GMT) List-Id: The branch 'vrull/heads/for-upstream' was updated to point to: 1b1c78c3157... riscv: Add support for strlen inline expansion It previously pointed to: 700a8672cef... riscv: Add support for strlen inline expansion Diff: !!! WARNING: THE FOLLOWING COMMITS ARE NO LONGER ACCESSIBLE (LOST): ------------------------------------------------------------------- 700a867... riscv: Add support for strlen inline expansion 7481d2c... riscv: Use by-pieces to do overlapping accesses in block_mo 9c50c4e... riscv: Move riscv_block_move_loop to separate file 5b68949... riscv: Enable overlap-by-pieces via tune param 00cd924... riscv: bitmanip/zbb: Add prefix/postfix and enable visiblit 7bd124d... RISC-V: Use .p2align for code-alignment 8182811... ifcvt: add if-conversion to conditional-zero instructions 1b64c20... RISC-V: Ventana-VT1 supports XVentanaCondOps 4d26578... RISC-V: Support immediates in XVentanaCondOps efc6969... RISC-V: Add instruction fusion (for ventana-vt1) b228f85... RISC-V: Add basic support for the Ventana-VT1 core 7ee9e75... RISC-V: Recognize bexti in negated if-conversion 92ef983... RISC-V: Recognize sign-extract + and cases for XVentanaCond 1368fa4... RISC-V: Support noce_try_store_flag_mask as vt.maskc 9422ef4... RISC-V: Generate vt.maskc on noce_try_store_flag_mask if ea64d45... RISC-V: Recognize xventanacondops extension 4f1ddbe... RISC-V: Handle "(a & twobits) == singlebit" in branches usi a4558d1... RISC-V: Use bseti/bclri/binvi to extend reach of ori/andi/x 81c0dc3... RISC-V: Replace zero_extendsidi2_shifted with generalized s f525996... ifcombine: fold two bit tests with different polarity 1a9164c... ifcombine: recognize single bit test of sign-bit 34865c7... RISC-V: Implement movmisalign to enable SLP 32dcd20... RISC-V: Optimise adding a (larger than simm12) constant to a34c0e9... RISC-V: No extensions for SImode min/max against safe const 110d704... RISC-V: Optimize branches testing a bit-range or a shifted c71897e... RISC-V: allow bseti on SImode without sign-extension 26071b5... RISC-V: Optimize slli(.uw)? + addw + zext.w into sh[123]add e378300... RISC-V: split to allow formation of sh[123]add before 32bit d0a7eb7... RISC-V: branch-(not)equals-zero compares against $zero Summary of changes (added commits): ----------------------------------- 1b1c78c... riscv: Add support for strlen inline expansion 5ea97a2... riscv: Use by-pieces to do overlapping accesses in block_mo e5670d7... riscv: Move riscv_block_move_loop to separate file 8f6a6b1... riscv: Enable overlap-by-pieces via tune param 74922e2... riscv: bitmanip/zbb: Add prefix/postfix and enable visiblit f709428... RISC-V: Use .p2align for code-alignment 457b5e7... ifcvt: add if-conversion to conditional-zero instructions abfa0c7... RISC-V: Ventana-VT1 supports XVentanaCondOps f2f4cda... RISC-V: Support immediates in XVentanaCondOps e0d5010... RISC-V: Add instruction fusion (for ventana-vt1) 042df39... RISC-V: Add basic support for the Ventana-VT1 core 337454d... RISC-V: Recognize bexti in negated if-conversion 9bedb1c... RISC-V: Recognize sign-extract + and cases for XVentanaCond 30f9ad1... RISC-V: Support noce_try_store_flag_mask as vt.maskc 2967ccf... RISC-V: Generate vt.maskc on noce_try_store_flag_mask if 9ef7c58... RISC-V: Recognize xventanacondops extension e5c49c6... RISC-V: Replace zero_extendsidi2_shifted with generalized s e480cf9... ifcombine: fold two bit tests with different polarity f9ddc80... ifcombine: recognize single bit test of sign-bit 015bb80... RISC-V: Implement movmisalign to enable SLP efd58b6... RISC-V: Optimise adding a (larger than simm12) constant to 8471d7e... RISC-V: No extensions for SImode min/max against safe const 800ff37... RISC-V: branch-(not)equals-zero compares against $zero 60d2bcc... RISC-V: Handle "(a & twobits) == singlebit" in branches usi (*) bc6beec... RISC-V: Use bseti/bclri/binvi to extend reach of ori/andi/x (*) 787ac95... RISC-V: Optimize slli(.uw)? + addw + zext.w into sh[123]add (*) 30c2d8d... RISC-V: split to allow formation of sh[123]add before 32bit (*) acbb5ef... RISC-V: Optimize branches testing a bit-range or a shifted (*) 23d9f62... RISC-V: allow bseti on SImode without sign-extension (*) 11543b2... libcpp: Avoid remapping filenames within directives (*) 59cc4da... Manually add entries for r13-4128. (*) 820c25c... Fortran: reject NULL actual argument without explicit inter (*) add8984... Daily bump. (*) f003fdf... Add another commit to ignore (*) ceba66e... Fix PR middle-end/107705: ICE after reclaration error (*) bd0c9d9... Fix PRs 106764, 106765, and 107307, all ICE after invalid r (*) acc205e... Fix testcase for architectures that use .srodata (*) 92905f6... aarch64: Fix LDAPURS assembly output (*) (*) This commit already exists in another branch. Because the reference `refs/vendors/vrull/heads/for-upstream' matches your hooks.email-new-commits-only configuration, no separate email is sent for this commit.