From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1923) id AFD483852C74; Fri, 18 Nov 2022 20:22:42 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org AFD483852C74 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1668802962; bh=Q/WkviCLCv9QUeZ+xGusBHA6d/g2AFef0e81cqLcHno=; h=From:To:Subject:Date:From; b=v0yl2fLX0qKqmP0FAkD1bLzJb7ELpdOAmlAd0Fj2QWJ9sACwZ4gyVLoWyGoUnSRP7 nBq3FEv31j1KBQZV0tzpmaRt8DZP8C272XfmCe8uM5aUXbIYRXVy7ONo3LzWL12k05 RmSVriUyO+0zyLmpIGJRM8nXlE6EwTETchAwR+eI= Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit From: Philipp Tomsich To: gcc-cvs@gcc.gnu.org Subject: [gcc(refs/vendors/vrull/heads/for-upstream)] RISC-V: Recognize xventanacondops extension X-Act-Checkin: gcc X-Git-Author: Philipp Tomsich X-Git-Refname: refs/vendors/vrull/heads/for-upstream X-Git-Oldrev: e5c49c608b2711b1735246050a3586bcb30de152 X-Git-Newrev: 9ef7c58fa23a2a995f67ea45b2d5d028e2a0dd27 Message-Id: <20221118202242.AFD483852C74@sourceware.org> Date: Fri, 18 Nov 2022 20:22:42 +0000 (GMT) List-Id: https://gcc.gnu.org/g:9ef7c58fa23a2a995f67ea45b2d5d028e2a0dd27 commit 9ef7c58fa23a2a995f67ea45b2d5d028e2a0dd27 Author: Philipp Tomsich Date: Sat Mar 5 23:19:03 2022 +0100 RISC-V: Recognize xventanacondops extension This adds the xventanacondops extension to the option parsing and as a default for the ventana-vt1 core: gcc/Changelog: * common/config/riscv/riscv-common.cc: Recognize "xventanacondops" as part of an architecture string. * config/riscv/riscv-opts.h (MASK_XVENTANACONDOPS): Define. (TARGET_XVENTANACONDOPS): Define. * config/riscv/riscv.opt: Add "riscv_xventanacondops". Cover-letter: RISC-V: Backend support for XVentanaCondOps/ZiCondops Both the XVentanaCondOps (a vendor-defined extension from Ventana Microsystems) and the proposed ZiCondOps extensions define a conditional-zero(-or-value) instruction, which is similar to the following C construct: rd = rc ? rs : 0 This functionality can be tied back into if-convertsion and also match some typical programming idioms. This series includes backend support for XVentanaCondops and infrastructure to handle conditional-zero constructions in if-conversion. Tested against SPEC CPU 2017. END Series-to: gcc-patches@gcc.gnu.org Series-cc: Palmer Dabbelt Series-cc: Vineet Gupta Series-cc: Christoph Muellner Series-cc: Kito Cheng Series-cc: Jeff Law Series-version: 3 Series-changes: 2 - Restore a (during rebase) dropped line to xventanacondops.md - Include the change to add xventanacondops to the VT1 code definition] as a separate patch. Series-changes: 3 - Address missed opportunities for forming CondOps. Diff: --- gcc/common/config/riscv/riscv-common.cc | 2 ++ gcc/config/riscv/riscv-opts.h | 3 +++ gcc/config/riscv/riscv.opt | 3 +++ 3 files changed, 8 insertions(+) diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc index 4b7f777c103..6b2bdda5feb 100644 --- a/gcc/common/config/riscv/riscv-common.cc +++ b/gcc/common/config/riscv/riscv-common.cc @@ -1247,6 +1247,8 @@ static const riscv_ext_flag_table_t riscv_ext_flag_table[] = {"svinval", &gcc_options::x_riscv_sv_subext, MASK_SVINVAL}, {"svnapot", &gcc_options::x_riscv_sv_subext, MASK_SVNAPOT}, + {"xventanacondops", &gcc_options::x_riscv_xventanacondops, MASK_XVENTANACONDOPS}, + {NULL, NULL, 0} }; diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h index 25fd85b09b1..84c987626bc 100644 --- a/gcc/config/riscv/riscv-opts.h +++ b/gcc/config/riscv/riscv-opts.h @@ -189,4 +189,7 @@ enum stack_protector_guard { ? 0 \ : 32 << (__builtin_popcount (riscv_zvl_flags) - 1)) +#define MASK_XVENTANACONDOPS (1 << 0) +#define TARGET_XVENTANACONDOPS ((riscv_xventanacondops & MASK_XVENTANACONDOPS) != 0) + #endif /* ! GCC_RISCV_OPTS_H */ diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt index 7c3ca48d1cc..9595078bdd4 100644 --- a/gcc/config/riscv/riscv.opt +++ b/gcc/config/riscv/riscv.opt @@ -233,6 +233,9 @@ int riscv_zm_subext TargetVariable int riscv_sv_subext +TargetVariable +int riscv_xventanacondops = 0 + Enum Name(isa_spec_class) Type(enum riscv_isa_spec_class) Supported ISA specs (for use with the -misa-spec= option):