From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1923) id C317B3852201; Fri, 18 Nov 2022 20:22:47 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org C317B3852201 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1668802967; bh=e7qwfGSBNfBboV/BiYZ2jVfBXrH7uqIoTmdz75eC7FI=; h=From:To:Subject:Date:From; b=a/9gfNBAYDhQJtYcBWk81kKpxhVeKLJT7i1MTpYahFTR9eyua/Afgkm7QCQiqW4Ss Gxwn2dEheixTIPdPuXxkuC9whKm9uwVogE9+GMOK2VeeN7RYWfiNuft+DHhBed4APb Of279F4s/hMJG/Jc3DL+nxEVb14QCRaWFwNYewiY= Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit From: Philipp Tomsich To: gcc-cvs@gcc.gnu.org Subject: [gcc(refs/vendors/vrull/heads/for-upstream)] RISC-V: Generate vt.maskc on noce_try_store_flag_mask if-conversion X-Act-Checkin: gcc X-Git-Author: Philipp Tomsich X-Git-Refname: refs/vendors/vrull/heads/for-upstream X-Git-Oldrev: 9ef7c58fa23a2a995f67ea45b2d5d028e2a0dd27 X-Git-Newrev: 2967ccf7e8a3b6846a867065c475832aaf0680f2 Message-Id: <20221118202247.C317B3852201@sourceware.org> Date: Fri, 18 Nov 2022 20:22:47 +0000 (GMT) List-Id: https://gcc.gnu.org/g:2967ccf7e8a3b6846a867065c475832aaf0680f2 commit 2967ccf7e8a3b6846a867065c475832aaf0680f2 Author: Philipp Tomsich Date: Sat Mar 5 23:21:10 2022 +0100 RISC-V: Generate vt.maskc on noce_try_store_flag_mask if-conversion Adds a pattern to map the output of noce_try_store_flag_mask if-conversion in the combiner onto vt.maskc; the input patterns supported are similar to the following: (set (reg/v/f:DI 75 [ ]) (and:DI (neg:DI (ne:DI (reg:DI 82) (const_int 0 [0]))) (reg/v/f:DI 75 [ ]))) This reduces dynamic instruction counts for the perlbench-workload in SPEC CPU2017 by 0.8230%, 0.4689%, and 0.2332% (respectively, for the each of the 3 workloads in the 'ref'-workload). To ensure that the combine-pass doesn't get confused about profitability, we recognize the idiom as requiring a single instruction when the XVentanaCondOps extension is present. gcc/ChangeLog: * config/riscv/riscv.cc (riscv_rtx_costs): Recognize idiom for vt.maskc as a single insn with TARGET_XVENTANACONDOPS. * config/riscv/riscv.md: Include xventanacondops.md. * config/riscv/xventanacondops.md: New file. gcc/testsuite/ChangeLog: * gcc.target/riscv/xventanacondops-ne-03.c: New test. * gcc.target/riscv/xventanacondops-ne-04.c: New test. Commit-changes: 2 - Ran whitespace-cleanup on xventanacondops-ne-03.c - Ran whitespace-cleanup on xventanacondops-ne-04.c Diff: --- gcc/config/riscv/riscv.cc | 14 ++++++++++ gcc/config/riscv/riscv.md | 1 + gcc/config/riscv/xventanacondops.md | 30 ++++++++++++++++++++++ .../gcc.target/riscv/xventanacondops-ne-03.c | 13 ++++++++++ .../gcc.target/riscv/xventanacondops-ne-04.c | 13 ++++++++++ 5 files changed, 71 insertions(+) diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index 9a4dad40193..1e82b743c15 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -2307,6 +2307,20 @@ riscv_rtx_costs (rtx x, machine_mode mode, int outer_code, int opno ATTRIBUTE_UN return false; case AND: + /* vt.maskc/vt.maskcn for XVentanaCondOps */ + if (TARGET_XVENTANACONDOPS && mode == word_mode + && GET_CODE (XEXP (x, 0)) == NEG) + { + rtx inner = XEXP (XEXP (x, 0), 0); + + if ((GET_CODE (inner) == EQ || GET_CODE (inner) == NE) + && CONST_INT_P (XEXP (inner, 1)) + && INTVAL (XEXP (inner, 1)) == 0) + { + *total = COSTS_N_INSNS (1); + return true; + } + } /* slli.uw pattern for zba. */ if (TARGET_ZBA && TARGET_64BIT && mode == DImode && GET_CODE (XEXP (x, 0)) == ASHIFT) diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md index 328e139705a..14db75faccd 100644 --- a/gcc/config/riscv/riscv.md +++ b/gcc/config/riscv/riscv.md @@ -3207,3 +3207,4 @@ (include "generic.md") (include "sifive-7.md") (include "vector.md") +(include "xventanacondops.md") diff --git a/gcc/config/riscv/xventanacondops.md b/gcc/config/riscv/xventanacondops.md new file mode 100644 index 00000000000..641cef0e44e --- /dev/null +++ b/gcc/config/riscv/xventanacondops.md @@ -0,0 +1,30 @@ +;; Machine description for X-Ventana-CondOps +;; Copyright (C) 2022 Free Software Foundation, Inc. + +;; This file is part of GCC. + +;; GCC is free software; you can redistribute it and/or modify +;; it under the terms of the GNU General Public License as published by +;; the Free Software Foundation; either version 3, or (at your option) +;; any later version. + +;; GCC is distributed in the hope that it will be useful, +;; but WITHOUT ANY WARRANTY; without even the implied warranty of +;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +;; GNU General Public License for more details. + +;; You should have received a copy of the GNU General Public License +;; along with GCC; see the file COPYING3. If not see +;; . + +(define_code_iterator eq_or_ne [eq ne]) +(define_code_attr n [(eq "n") (ne "")]) + +(define_insn "*vt.maskc" + [(set (match_operand:DI 0 "register_operand" "=r") + (and:DI (neg:DI (eq_or_ne:DI + (match_operand:DI 1 "register_operand" "r") + (const_int 0))) + (match_operand:DI 2 "register_operand" "r")))] + "TARGET_XVENTANACONDOPS" + "vt.maskc\t%0,%2,%1") diff --git a/gcc/testsuite/gcc.target/riscv/xventanacondops-ne-03.c b/gcc/testsuite/gcc.target/riscv/xventanacondops-ne-03.c new file mode 100644 index 00000000000..4a762a1ed61 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/xventanacondops-ne-03.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_xventanacondops -mabi=lp64 -mtune=thead-c906" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-O1" "-Os" "-Oz" } } */ + +long long ne3(long long a, long long b) +{ + if (a != 0) + return b; + + return 0; +} + +/* { dg-final { scan-assembler-times "vt.maskc" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/xventanacondops-ne-04.c b/gcc/testsuite/gcc.target/riscv/xventanacondops-ne-04.c new file mode 100644 index 00000000000..18b35ac7070 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/xventanacondops-ne-04.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_xventanacondops -mabi=lp64 -mtune=thead-c906" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ + +long long ne4(long long a, long long b) +{ + if (a != 0) + return 0; + + return b; +} + +/* { dg-final { scan-assembler-times "vt.maskcn" 1 } } */