From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1923) id 412743852208; Fri, 18 Nov 2022 20:23:18 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 412743852208 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1668802998; bh=Ji9BTaIooTxkoJQw1N1nEmQJxpnqj6RH6KpkKwC9kwA=; h=From:To:Subject:Date:From; b=XqUSczvAi4WPIOkDF1pmQs4qcPqMFilRGDxfJKN93vnTv9Zv9FSOTiZtx3rNfGx1I 4a6x/9HiMF0m+Ve7EeZUimvII3ibvWG+7clKhGbwzLRIinJ1nX90gocFLHosIPZg+I jYGsr+aOgil25eD2+rgGAuHjBfSbsEGvDECq3evk= Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit From: Philipp Tomsich To: gcc-cvs@gcc.gnu.org Subject: [gcc(refs/vendors/vrull/heads/for-upstream)] RISC-V: Support immediates in XVentanaCondOps X-Act-Checkin: gcc X-Git-Author: Philipp Tomsich X-Git-Refname: refs/vendors/vrull/heads/for-upstream X-Git-Oldrev: e0d50105e018f94b7f257a15b62ae0a0daa55b9a X-Git-Newrev: f2f4cda943d0346b12598da48b1d0b87f673e5b3 Message-Id: <20221118202318.412743852208@sourceware.org> Date: Fri, 18 Nov 2022 20:23:18 +0000 (GMT) List-Id: https://gcc.gnu.org/g:f2f4cda943d0346b12598da48b1d0b87f673e5b3 commit f2f4cda943d0346b12598da48b1d0b87f673e5b3 Author: Philipp Tomsich Date: Tue Apr 26 16:03:58 2022 +0200 RISC-V: Support immediates in XVentanaCondOps When if-conversion encounters sequences using immediates, the sequences can't trivially map back onto vt.maskc/vt.maskcn (even if benefitial) due to vt.maskc and vt.maskcn not having immediate forms. This adds a splitter to rewrite opportunities for XVentanaCondOps that operate on an immediate by first putting the immediate into a register to enable the non-immediate vt.maskc/vt.maskcn instructions to operate on the value. Consider code, such as long func2 (long a, long c) { if (c) a = 2; else a = 5; return a; } which will be converted to func2: seqz a0,a2 neg a0,a0 andi a0,a0,3 addi a0,a0,2 ret Following this change, we generate li a0,3 vt.maskcn a0,a0,a2 addi a0,a0,2 ret This commit also introduces a simple unit test for if-conversion with immediate (literal) values as the sources for simple sets in the THEN and ELSE blocks. The test checks that Ventana's conditional mask instruction (vt.maskc) is emitted as part of the resultant branchless instruction sequence. gcc/ChangeLog: * config/riscv/xventanacondops.md: Support immediates for vt.maskc/vt.maskcn through a splitter. gcc/testsuite/ChangeLog: * gcc.target/riscv/xventanacondops-ifconv-imm.c: New test. Signed-off-by: Philipp Tomsich Reviewed-by: Henry Brausen Commit-notes: Ref #204 END Diff: --- gcc/config/riscv/xventanacondops.md | 24 ++++++++++++++++++++-- .../gcc.target/riscv/xventanacondops-ifconv-imm.c | 19 +++++++++++++++++ 2 files changed, 41 insertions(+), 2 deletions(-) diff --git a/gcc/config/riscv/xventanacondops.md b/gcc/config/riscv/xventanacondops.md index 1e01fe1c6de..5128813e1ea 100644 --- a/gcc/config/riscv/xventanacondops.md +++ b/gcc/config/riscv/xventanacondops.md @@ -29,6 +29,26 @@ "TARGET_XVENTANACONDOPS" "vt.maskc\t%0,%2,%1") +;; XVentanaCondOps does not have immediate forms, so we need to do extra +;; work to support these: if we encounter a vt.maskc/n with an immediate, +;; we split this into a load-immediate followed by a vt.maskc/n. +(define_split + [(set (match_operand:DI 0 "register_operand") + (and:DI (neg:DI (match_operator:DI 1 "equality_operator" + [(match_operand:DI 2 "register_operand") + (const_int 0)])) + (match_operand:DI 3 "immediate_operand"))) + (clobber (match_operand:DI 4 "register_operand"))] + "TARGET_XVENTANACONDOPS" + [(set (match_dup 4) (match_dup 3)) + (set (match_dup 0) (and:DI (neg:DI (match_dup 1)) + (match_dup 4)))] +{ + /* Eliminate the clobber/temporary, if it is not needed. */ + if (!rtx_equal_p (operands[0], operands[2])) + operands[4] = operands[0]; +}) + ;; Make order operators digestible to the vt.maskc logic by ;; wrapping their result in a comparison against (const_int 0). @@ -37,7 +57,7 @@ [(set (match_operand:X 0 "register_operand") (and:X (neg:X (match_operator:X 1 "anyge_operator" [(match_operand:X 2 "register_operand") - (match_operand:X 3 "register_operand")])) + (match_operand:X 3 "arith_operand")])) (match_operand:X 4 "register_operand"))) (clobber (match_operand:X 5 "register_operand"))] "TARGET_XVENTANACONDOPS" @@ -54,7 +74,7 @@ [(set (match_operand:X 0 "register_operand") (and:X (neg:X (match_operator:X 1 "anygt_operator" [(match_operand:X 2 "register_operand") - (match_operand:X 3 "register_operand")])) + (match_operand:X 3 "arith_operand")])) (match_operand:X 4 "register_operand"))) (clobber (match_operand:X 5 "register_operand"))] "TARGET_XVENTANACONDOPS" diff --git a/gcc/testsuite/gcc.target/riscv/xventanacondops-ifconv-imm.c b/gcc/testsuite/gcc.target/riscv/xventanacondops-ifconv-imm.c new file mode 100644 index 00000000000..0012e7b669c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/xventanacondops-ifconv-imm.c @@ -0,0 +1,19 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_xventanacondops -mabi=lp64" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */ + +/* Each function below should emit a vt.maskcn instruction */ + +long +foo0 (long a, long b, long c) +{ + if (c) + a = 0; + else + a = 5; + return a; +} + +/* { dg-final { scan-assembler-times "vt.maskcn\t" 1 } } */ +/* { dg-final { scan-assembler-not "beqz\t" } } */ +/* { dg-final { scan-assembler-not "bnez\t" } } */