From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1923) id 69BD2385222F; Fri, 18 Nov 2022 20:23:23 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 69BD2385222F DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1668803003; bh=cFz5a4UEbFAh4/K+A3kP7FF7Q3fkF6DPYSWooqEtMgY=; h=From:To:Subject:Date:From; b=LfT0JmIkvBctHvcRaKLWlxA3JaTQPafENxDXFzzYVy/2KjpfV9XMfhcOJUfkLjkks cxoUu5u8D6SMorwF4okQjV/GwO2h0xJu1wI/Bi3BufXlK1U8Y5hKBb0X9HgCP4exw0 cXQy2uMAHLyLcLpoZzZPBJ8j9PUYkvDMh/CeGStc= Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit From: Philipp Tomsich To: gcc-cvs@gcc.gnu.org Subject: [gcc(refs/vendors/vrull/heads/for-upstream)] RISC-V: Ventana-VT1 supports XVentanaCondOps X-Act-Checkin: gcc X-Git-Author: Philipp Tomsich X-Git-Refname: refs/vendors/vrull/heads/for-upstream X-Git-Oldrev: f2f4cda943d0346b12598da48b1d0b87f673e5b3 X-Git-Newrev: abfa0c7229e0416a2928e9fc9310b579ae38cd40 Message-Id: <20221118202323.69BD2385222F@sourceware.org> Date: Fri, 18 Nov 2022 20:23:23 +0000 (GMT) List-Id: https://gcc.gnu.org/g:abfa0c7229e0416a2928e9fc9310b579ae38cd40 commit abfa0c7229e0416a2928e9fc9310b579ae38cd40 Author: Philipp Tomsich Date: Sun Nov 13 21:50:24 2022 +0100 RISC-V: Ventana-VT1 supports XVentanaCondOps gcc/ChangeLog: * config/riscv/riscv-cores.def (RISCV_CORE): Update the Ventana-VT1 definition to include the xventanacondops extension. Commit-changes: 2 - New in v2. Diff: --- gcc/config/riscv/riscv-cores.def | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/gcc/config/riscv/riscv-cores.def b/gcc/config/riscv/riscv-cores.def index aef1e92ae24..9e38e9dc72e 100644 --- a/gcc/config/riscv/riscv-cores.def +++ b/gcc/config/riscv/riscv-cores.def @@ -74,6 +74,6 @@ RISCV_CORE("sifive-s76", "rv64imafdc", "sifive-7-series") RISCV_CORE("sifive-u54", "rv64imafdc", "sifive-5-series") RISCV_CORE("sifive-u74", "rv64imafdc", "sifive-7-series") -RISCV_CORE("ventana-vt1", "rv64imafdc_zba_zbb_zbc_zbs_zifencei", "ventana-vt1") +RISCV_CORE("ventana-vt1", "rv64imafdc_zba_zbb_zbc_zbs_zifencei_xventanacondops", "ventana-vt1") #undef RISCV_CORE