[gcc(refs/vendors/vrull/heads/for-upstream)] ifcvt: add if-conversion to conditional-zero instructions

[Philipp Tomsich <ptomsich@gcc.gnu.org>]

https://gcc.gnu.org/g:457b5e7332a9d4eadd22b931b1e69d1432ffadc2

commit 457b5e7332a9d4eadd22b931b1e69d1432ffadc2
Author: Philipp Tomsich <philipp.tomsich@vrull.eu>
Date:   Thu Nov 10 14:11:36 2022 +0100

    ifcvt: add if-conversion to conditional-zero instructions
    
    Some architectures, as it the case on RISC-V with the proposed
    ZiCondOps and the vendor-defined XVentanaCondOps, define a
    conditional-zero instruction that is equivalent to:
     - the positive form:  rd = (rc != 0) ? rs : 0
     - the negated form:   rd = (rc == 0) ? rs : 0
    
    While noce_try_store_flag_mask will somewhat work for this case, it
    will generate a number of atomic RTX that will misdirect the cost
    calculation and may be too long (i.e., 4 RTX and more) to successfully
    merge at combine-time.
    
    Instead, we add two new transforms that attempt to build up what we
    define as the canonical form of a conditional-zero expression:
    
      (set (match_operand 0 "register_operand" "=r")
           (and (neg (eq_or_ne (match_operand 1 "register_operand" "r")
                               (const_int 0)))
                (match_operand 2 "register_operand" "r")))
    
    Architectures that provide a conditional-zero are thus expected to
    define an instruction matching this pattern in their backend.
    
    Based on this, we support the following cases:
     - noce_try_condzero:
          a ? a : b
          a ? b : 0  (and then/else swapped)
         !a ? b : 0  (and then/else swapped)
     - noce_try_condzero_arith:
         conditional-plus, conditional-minus, conditional-and,
         conditional-or, conditional-xor, conditional-shift,
         conditional-and
    
    Given that this is hooked into the CE passes, it is less powerful than
    a tree-pass (e.g., it can not transform cases where an extension, such
    as for uint16_t operations is in either the then or else-branch
    together with the arithmetic) but already covers a good array of cases
    and triggers across SPEC CPU 2017.
    Adding transofmrations in a tree pass will be considered as a future
    improvement.
    
    gcc/ChangeLog:
    
            * ifcvt.cc (noce_emit_insn): Add prototype.
            (noce_emit_condzero): Helper for noce_try_condzero and
            noce_try_condzero_arith transforms.
            (noce_try_condzero): New transform.
            (noce_try_condzero_arith): New transform for conditional
            arithmetic that can be built up by exploiting that the
            conditional-zero instruction will inject 0, which acts
            as the neutral element for operations.
            (noce_process_if_block): Call noce_try_condzero and
            noce_try_condzero_arith.
    
    gcc/testsuite/ChangeLog:
    
            * gcc.target/riscv/xventanacondops-and-01.c: New test.
            * gcc.target/riscv/xventanacondops-and-02.c: New test.
            * gcc.target/riscv/xventanacondops-eq-01.c: New test.
            * gcc.target/riscv/xventanacondops-eq-02.c: New test.
            * gcc.target/riscv/xventanacondops-lt-01.c: New test.
            * gcc.target/riscv/xventanacondops-ne-01.c: New test.
            * gcc.target/riscv/xventanacondops-xor-01.c: New test.
    
    Commit-changes: 2
    - Ran whitespace-cleanup on xventanacondops-ne-01.c.

Diff:
---
 gcc/ifcvt.cc                                       | 214 +++++++++++++++++++++
 .../gcc.target/riscv/xventanacondops-and-01.c      |  16 ++
 .../gcc.target/riscv/xventanacondops-and-02.c      |  15 ++
 .../gcc.target/riscv/xventanacondops-eq-01.c       |  11 ++
 .../gcc.target/riscv/xventanacondops-eq-02.c       |  14 ++
 .../gcc.target/riscv/xventanacondops-lt-01.c       |  16 ++
 .../gcc.target/riscv/xventanacondops-ne-01.c       |  10 +
 .../gcc.target/riscv/xventanacondops-xor-01.c      |  14 ++
 8 files changed, 310 insertions(+)

diff --git a/gcc/ifcvt.cc b/gcc/ifcvt.cc
index eb8efb89a89..41c58876d05 100644
--- a/gcc/ifcvt.cc
+++ b/gcc/ifcvt.cc
@@ -97,6 +97,7 @@ static int find_if_case_2 (basic_block, edge, edge);
 static int dead_or_predicable (basic_block, basic_block, basic_block,
 			       edge, int);
 static void noce_emit_move_insn (rtx, rtx);
+static rtx_insn *noce_emit_insn (rtx);
 static rtx_insn *block_has_only_trap (basic_block);
 static void need_cmov_or_rewire (basic_block, hash_set<rtx_insn *> *,
 				 hash_map<rtx_insn *, int> *);
@@ -787,6 +788,9 @@ static rtx noce_get_alt_condition (struct noce_if_info *, rtx, rtx_insn **);
 static int noce_try_minmax (struct noce_if_info *);
 static int noce_try_abs (struct noce_if_info *);
 static int noce_try_sign_mask (struct noce_if_info *);
+static rtx noce_emit_condzero (struct noce_if_info *, rtx, bool = false);
+static int noce_try_condzero (struct noce_if_info *);
+static int noce_try_condzero_arith (struct noce_if_info *);
 
 /* Return the comparison code for reversed condition for IF_INFO,
    or UNKNOWN if reversing the condition is not possible.  */
@@ -1664,6 +1668,212 @@ noce_try_addcc (struct noce_if_info *if_info)
   return FALSE;
 }
 
+/* Helper to noce_try_condzero: cond ? a : 0. */
+static rtx
+noce_emit_condzero (struct noce_if_info *if_info, rtx a, bool reverse)
+{
+  /* The canonical form for a conditional-zero-or-value is:
+       (set (match_operand 0 "register_operand" "=r")
+	    (and (neg (eq_or_ne (match_operand 1 "register_operand" "r")
+				(const_int 0)))
+		 (match_operand 2 "register_operand" "r")))
+   */
+
+  machine_mode opmode = GET_MODE (if_info->x);
+  enum rtx_code code = GET_CODE (if_info->cond);
+  rtx cond;
+  rtx op_a = XEXP (if_info->cond, 0);
+  rtx op_b = XEXP (if_info->cond, 1);
+
+  /* If it is not a EQ/NE comparison against const0_rtx, canonicalize
+     by first synthesizing a truth-value and then building a NE
+     condition around it. */
+  if ((code != EQ && code != NE) || XEXP (if_info->cond, 1) != const0_rtx)
+    {
+      rtx tmp = gen_reg_rtx (opmode);
+
+      start_sequence ();
+      cond = gen_rtx_fmt_ee (code, opmode, op_a, op_b);
+      if (!noce_emit_insn (gen_rtx_SET (tmp, cond)))
+	{
+	  end_sequence ();
+
+	  /* If we can't emit this pattern, try to reverse it and
+	     invert the polarity of the second test. */
+	  start_sequence ();
+	  cond = gen_rtx_fmt_ee (reverse_condition (code), opmode, op_a, op_b);
+	  if (!noce_emit_insn (gen_rtx_SET (tmp, cond))) {
+	    end_sequence ();
+	    return NULL_RTX;
+	  }
+
+	  /* We have recovered by reversing the first comparison,
+	     so we need change the second one around as well... */
+	  reverse = !reverse;
+	}
+      rtx_insn *seq = get_insns ();
+      end_sequence ();
+      emit_insn (seq);
+
+      /* Set up the second comparison that will be embedded in the
+	 canonical conditional-zero-or-value RTX. */
+      code = NE;
+      op_a = tmp;
+      op_b = const0_rtx;
+    }
+
+  cond = gen_rtx_fmt_ee (reverse ? reverse_condition (code) : code,
+			 opmode, op_a, op_b);
+
+  /* Build (and (neg (eq_or_ne ... const0_rtx)) (reg <a>)) */
+  rtx target = gen_reg_rtx (opmode);
+  rtx czero = gen_rtx_AND (opmode, gen_rtx_NEG (opmode, cond), a);
+  noce_emit_move_insn (target, czero);
+
+  return target;
+}
+
+/* Use a conditional-zero instruction for "if (test) x = 0;", if available. */
+static int
+noce_try_condzero (struct noce_if_info *if_info)
+{
+  rtx target;
+  rtx_insn *seq;
+  int reversep = 0;
+  rtx orig_b = NULL_RTX;
+  rtx cond = if_info->cond;
+  enum rtx_code code = GET_CODE (cond);
+  rtx cond_arg0 = XEXP (cond, 0);
+  rtx cond_arg1 = XEXP (cond, 1);
+
+  if (!noce_simple_bbs (if_info))
+    return FALSE;
+
+  /* We may encounter the form "(a != 0) ? a : b", which can be
+     simplified to "a | ((a != 0) ? 0 : b)". */
+  if (code == NE && cond_arg1 == const0_rtx &&
+      REG_P (if_info->b) && rtx_equal_p (if_info->b, cond_arg0))
+    {
+      orig_b = if_info->b;
+      if_info->b = const0_rtx;
+    }
+
+  /* We may encounter the form "(a != 0) ? b : a", which can be
+     simplied to "(a != 0) ? b : 0". */
+  if (code == EQ && cond_arg1 == const0_rtx &&
+      REG_P (if_info->b) && rtx_equal_p (if_info->b, cond_arg0))
+    {
+      /* We know that cond_arg0 is const_0, if the THEN branch is
+	 taken... so if it is the same as if_info->b (yes, things are
+	 backwards!), we can rewrite it with that knowledge.  */
+      if_info->b = const0_rtx;
+    }
+
+  start_sequence ();
+
+  if ((if_info->a == const0_rtx
+       && (REG_P (if_info->b) || rtx_equal_p (if_info->b, if_info->x)))
+      || ((reversep = (noce_reversed_cond_code (if_info) != UNKNOWN))
+	  && if_info->b == const0_rtx
+	  && (REG_P (if_info->a) || rtx_equal_p (if_info->a, if_info->x))))
+    {
+      target = noce_emit_condzero(if_info,
+				  reversep ? if_info->a : if_info->b,
+				  reversep);
+
+      if (orig_b && target)
+	target = expand_simple_binop (GET_MODE (if_info->x), IOR, orig_b,
+				      target, if_info->x, 0, OPTAB_WIDEN);
+
+      if (target)
+	{
+	  if (target != if_info->x)
+	    noce_emit_move_insn (if_info->x, target);
+
+	  seq = end_ifcvt_sequence (if_info);
+	  if (!seq || !targetm.noce_conversion_profitable_p (seq, if_info))
+	    return FALSE;
+
+	  emit_insn_before_setloc (seq, if_info->jump,
+				   INSN_LOCATION (if_info->insn_a));
+	  if_info->transform_name = "noce_try_condzero";
+
+	  return TRUE;
+	}
+    }
+
+  end_sequence ();
+
+  return FALSE;
+}
+
+/* Convert "if (test) x op= a;" to a branchless sequence using the
+   canonical form for a conditional-zero. */
+static int
+noce_try_condzero_arith (struct noce_if_info *if_info)
+{
+  rtx target;
+  rtx_insn *seq;
+  rtx_code op = GET_CODE (if_info->a);
+  const rtx arg0 = XEXP (if_info->a, 0);
+  const rtx arg1 = XEXP (if_info->a, 1);
+
+  if (!noce_simple_bbs (if_info))
+    return FALSE;
+
+  /* Check for no else condition.  */
+  if (!rtx_equal_p (if_info->x, if_info->b))
+    return FALSE;
+
+  if (op != PLUS && op != MINUS && op != IOR && op != XOR &&
+      op != ASHIFT && op != ASHIFTRT && op != LSHIFTRT && op != AND)
+    return FALSE;
+
+  if (!rtx_equal_p (if_info->x, arg0))
+    return FALSE;
+
+  start_sequence ();
+
+  target = noce_emit_condzero(if_info, arg1, op != AND ? true : false);
+
+  if (target)
+    {
+      rtx op1 = if_info->x;
+      
+      if (op == AND)
+	{
+	  /* Emit "tmp = x & val;" followed by "tmp |= !cond ? x : 0;" */
+	  op1 = expand_simple_binop (GET_MODE (if_info->x), AND, op1,
+				     arg1, NULL_RTX, 0, OPTAB_WIDEN);
+	  op = IOR;
+	}
+
+      if (op1)
+	target = expand_simple_binop (GET_MODE (if_info->x), op, op1,
+				      target, if_info->x, 0, OPTAB_WIDEN);
+    }
+
+  if (target)
+    {
+      if (target != if_info->x)
+	noce_emit_move_insn (if_info->x, target);
+
+      seq = end_ifcvt_sequence (if_info);
+      if (!seq || !targetm.noce_conversion_profitable_p (seq, if_info))
+	return FALSE;
+
+      emit_insn_before_setloc(seq, if_info->jump,
+			      INSN_LOCATION(if_info->insn_a));
+      if_info->transform_name = "noce_try_condzero_arith";
+
+      return TRUE;
+    }
+
+  end_sequence ();
+
+  return FALSE;
+}
+
 /* Convert "if (test) x = 0;" to "x &= -(test == 0);"  */
 
 static int
@@ -3967,8 +4177,12 @@ noce_process_if_block (struct noce_if_info *if_info)
     {
       if (noce_try_addcc (if_info))
 	goto success;
+      if (noce_try_condzero (if_info))
+	goto success;
       if (noce_try_store_flag_mask (if_info))
 	goto success;
+      if (noce_try_condzero_arith (if_info))
+	goto success;
       if (HAVE_conditional_move
 	  && noce_try_cmove_arith (if_info))
 	goto success;
diff --git a/gcc/testsuite/gcc.target/riscv/xventanacondops-and-01.c b/gcc/testsuite/gcc.target/riscv/xventanacondops-and-01.c
new file mode 100644
index 00000000000..9b26cdf0513
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/xventanacondops-and-01.c
@@ -0,0 +1,16 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_xventanacondops -mabi=lp64" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
+
+long and1(long a, long b, long c, long d)
+{
+  if (c < d)
+    a &= b;
+
+  return a;
+}
+
+/* { dg-final { scan-assembler-times "and\t" 1 } } */
+/* { dg-final { scan-assembler-times "slt" 1 } } */
+/* { dg-final { scan-assembler-times "vt.maskcn" 1 } } */
+/* { dg-final { scan-assembler-times "or\t" 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/xventanacondops-and-02.c b/gcc/testsuite/gcc.target/riscv/xventanacondops-and-02.c
new file mode 100644
index 00000000000..66d2ec10211
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/xventanacondops-and-02.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_xventanacondops -mabi=lp64" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
+
+int and2(int a, int b, long c)
+{
+  if (c)
+    a &= b;
+
+  return a;
+}
+
+/* { dg-final { scan-assembler-times "and\t" 1 } } */
+/* { dg-final { scan-assembler-times "vt.maskcn" 1 } } */
+/* { dg-final { scan-assembler-times "or\t" 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/xventanacondops-eq-01.c b/gcc/testsuite/gcc.target/riscv/xventanacondops-eq-01.c
new file mode 100644
index 00000000000..bc877d9e81b
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/xventanacondops-eq-01.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_xventanacondops -mabi=lp64" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" } } */
+
+long
+eq1 (long a, long b)
+{
+  return (a == 0) ? b : 0;
+}
+
+/* { dg-final { scan-assembler-times "vt.maskcn" 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/xventanacondops-eq-02.c b/gcc/testsuite/gcc.target/riscv/xventanacondops-eq-02.c
new file mode 100644
index 00000000000..28317613ba8
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/xventanacondops-eq-02.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_xventanacondops -mabi=lp64" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" } } */
+
+long
+eq2 (long a, long b)
+{
+  if (a == 0)
+    return b;
+
+  return 0;
+}
+
+/* { dg-final { scan-assembler-times "vt.maskcn" 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/xventanacondops-lt-01.c b/gcc/testsuite/gcc.target/riscv/xventanacondops-lt-01.c
new file mode 100644
index 00000000000..18762ee2bd0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/xventanacondops-lt-01.c
@@ -0,0 +1,16 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_xventanacondops -mabi=lp64" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
+
+long long sink (long long);
+
+long long lt3 (long long a, long long b)
+{
+  if (a < b) 
+    b = 0;
+
+  return sink(b);
+}
+
+/* { dg-final { scan-assembler-times "vt.maskcn\t" 1 } } */
+/* { dg-final { scan-assembler-times "slt\t" 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/xventanacondops-ne-01.c b/gcc/testsuite/gcc.target/riscv/xventanacondops-ne-01.c
new file mode 100644
index 00000000000..be8375ba5cf
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/xventanacondops-ne-01.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_xventanacondops -mabi=lp64" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" } } */
+
+long long ne1(long long a, long long b)
+{
+  return (a != 0) ? b : 0;
+}
+
+/* { dg-final { scan-assembler-times "vt.maskc" 1 } } */
diff --git a/gcc/testsuite/gcc.target/riscv/xventanacondops-xor-01.c b/gcc/testsuite/gcc.target/riscv/xventanacondops-xor-01.c
new file mode 100644
index 00000000000..43020790a22
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/xventanacondops-xor-01.c
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-options "-march=rv64gc_xventanacondops -mabi=lp64" } */
+/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" "-Os" "-Oz" } } */
+
+long xor1(long crc, long poly)
+{
+  if (crc & 1)
+    crc ^= poly;
+
+  return crc;
+}
+
+/* { dg-final { scan-assembler-times "vt.maskc" 1 } } */
+/* { dg-final { scan-assembler-times "xor\t" 1 } } */