From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1923) id 897E63853D7F; Fri, 18 Nov 2022 20:26:04 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 897E63853D7F DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1668803164; bh=uvusm1AYRE1HM/O/UVeL9F6cdjxBpWMTShpfIFBIsFY=; h=From:To:Subject:Date:From; b=tIK7lv/Qw/0YXFJ5QKMlEz/mWPrhHot+ptrG2jBYb9TAerJ7Dt6RUDqqzl1AnOoc2 d+V+yqhoV6NeVY3/WwnsvqnOGtfoMxO5Lm75jmUa4yKPU/tY4ujqPT4Fe5hINzT5Xi tK+Zy6HdcuHTnc11lKgLUwL944PDLxPID4XV6wSE= Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit From: Philipp Tomsich To: gcc-cvs@gcc.gnu.org Subject: [gcc(refs/vendors/vrull/heads/for-upstream)] RISC-V: Recognize bexti in negated if-conversion X-Act-Checkin: gcc X-Git-Author: Philipp Tomsich X-Git-Refname: refs/vendors/vrull/heads/for-upstream X-Git-Oldrev: 95fbae489fa57652b7037239d66bf21b737801ee X-Git-Newrev: 95e8d5dcf2d6395d87191ddd82b3022149df7533 Message-Id: <20221118202604.897E63853D7F@sourceware.org> Date: Fri, 18 Nov 2022 20:26:04 +0000 (GMT) List-Id: https://gcc.gnu.org/g:95e8d5dcf2d6395d87191ddd82b3022149df7533 commit 95e8d5dcf2d6395d87191ddd82b3022149df7533 Author: Philipp Tomsich Date: Wed Mar 30 00:01:30 2022 +0200 RISC-V: Recognize bexti in negated if-conversion While the positive case "if ((bits >> SHAMT) & 1)" for SHAMT 0..10 can trigger conversion into efficient branchless sequences - with Zbs (bexti + neg + and) - with XVentanaCondOps (andi + vt.maskc) the inverted/negated case results in andi a5,a0,1024 seqz a5,a5 neg a5,a5 and a5,a5,a1 due to how the sequence presents to the combine pass. This adds an additional splitter to reassociate the polarity reversed case into bexti + addi, if Zbs is present. gcc/ChangeLog: * config/riscv/xventanacondops.md: Add split to reassociate "andi + seqz + neg" into "bexti + addi". Commit-changes: 2 - Removed spurious empty line at the end of xventanacondops.md. Diff: --- gcc/config/riscv/xventanacondops.md | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/gcc/config/riscv/xventanacondops.md b/gcc/config/riscv/xventanacondops.md index f2eb886659f..1e01fe1c6de 100644 --- a/gcc/config/riscv/xventanacondops.md +++ b/gcc/config/riscv/xventanacondops.md @@ -123,3 +123,13 @@ { operands[2] = GEN_INT(1 << UINTVAL(operands[2])); }) + +(define_split + [(set (match_operand:X 0 "register_operand") + (neg:X (eq:X (zero_extract:X (match_operand:X 1 "register_operand") + (const_int 1) + (match_operand 2 "immediate_operand")) + (const_int 0))))] + "!TARGET_XVENTANACONDOPS && TARGET_ZBS" + [(set (match_dup 0) (zero_extract:X (match_dup 1) (const_int 1) (match_dup 2))) + (set (match_dup 0) (plus:X (match_dup 0) (const_int -1)))])