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From: hongtao Liu <liuhongt@gcc.gnu.org> To: gcc-cvs@gcc.gnu.org Subject: [gcc r13-4225] Guard 64/32-bit vector move patterns with ix86_hard_reg_move_ok. Date: Tue, 22 Nov 2022 04:50:24 +0000 (GMT) [thread overview] Message-ID: <20221122045024.975BC3858298@sourceware.org> (raw) https://gcc.gnu.org/g:d5fce9f6c15554a7d5bfbbcd1740200f1d32fa15 commit r13-4225-gd5fce9f6c15554a7d5bfbbcd1740200f1d32fa15 Author: liuhongt <hongtao.liu@intel.com> Date: Mon Nov 21 16:09:13 2022 +0800 Guard 64/32-bit vector move patterns with ix86_hard_reg_move_ok. gcc/ChangeLog: * config/i386/mmx.md (*mov<mode>_internal): Add ix86_hard_reg_move_ok to condition. Diff: --- gcc/config/i386/mmx.md | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/gcc/config/i386/mmx.md b/gcc/config/i386/mmx.md index d5134cc351e..63aff287795 100644 --- a/gcc/config/i386/mmx.md +++ b/gcc/config/i386/mmx.md @@ -133,7 +133,8 @@ (match_operand:MMXMODE 1 "nonimm_or_0_operand" "rCo,rC,C,rm,rC,C ,!y,m ,?!y,?!y,r ,C,v,m,v,v,r,*x,!y"))] "(TARGET_MMX || TARGET_MMX_WITH_SSE) - && !(MEM_P (operands[0]) && MEM_P (operands[1]))" + && !(MEM_P (operands[0]) && MEM_P (operands[1])) + && ix86_hardreg_mov_ok (operands[0], operands[1])" { switch (get_attr_type (insn)) { @@ -286,7 +287,8 @@ "=r ,m ,v,v,v,m,r,v") (match_operand:V_32 1 "general_operand" "rmC,rC,C,v,m,v,v,r"))] - "!(MEM_P (operands[0]) && MEM_P (operands[1]))" + "!(MEM_P (operands[0]) && MEM_P (operands[1])) + && ix86_hardreg_mov_ok (operands[0], operands[1])" { switch (get_attr_type (insn)) {
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