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From: Tamar Christina <tnfchris@gcc.gnu.org> To: gcc-cvs@gcc.gnu.org Subject: [gcc r13-4303] sve2: Fix expansion of division [PR107830] Date: Fri, 25 Nov 2022 12:58:08 +0000 (GMT) [thread overview] Message-ID: <20221125125808.7611238532C2@sourceware.org> (raw) https://gcc.gnu.org/g:71f3036b8a83da7fb559923bc80687ea1dabe14a commit r13-4303-g71f3036b8a83da7fb559923bc80687ea1dabe14a Author: Tamar Christina <tamar.christina@arm.com> Date: Fri Nov 25 12:57:24 2022 +0000 sve2: Fix expansion of division [PR107830] SVE has an actual division optab, and when using -Os we don't optimize the division away. This means that we need to distinguish between a div which we can optimize and one we cannot even during expansion. gcc/ChangeLog: PR target/107830 * config/aarch64/aarch64.cc (aarch64_vectorize_can_special_div_by_constant): Check validity during codegen phase as well. gcc/testsuite/ChangeLog: PR target/107830 * gcc.target/aarch64/sve2/pr107830-1.c: New test. * gcc.target/aarch64/sve2/pr107830-2.c: New test. Diff: --- gcc/config/aarch64/aarch64.cc | 15 ++++++++++----- gcc/testsuite/gcc.target/aarch64/sve2/pr107830-1.c | 13 +++++++++++++ gcc/testsuite/gcc.target/aarch64/sve2/pr107830-2.c | 12 ++++++++++++ 3 files changed, 35 insertions(+), 5 deletions(-) diff --git a/gcc/config/aarch64/aarch64.cc b/gcc/config/aarch64/aarch64.cc index 15d478c77ce..14f1994adf3 100644 --- a/gcc/config/aarch64/aarch64.cc +++ b/gcc/config/aarch64/aarch64.cc @@ -24351,12 +24351,17 @@ aarch64_vectorize_can_special_div_by_constant (enum tree_code code, if ((flags & VEC_ANY_SVE) && !TARGET_SVE2) return false; + int pow = wi::exact_log2 (cst + 1); + auto insn_code = maybe_code_for_aarch64_bitmask_udiv3 (TYPE_MODE (vectype)); + /* SVE actually has a div operator, we may have gotten here through + that route. */ + if (pow != (int) (element_precision (vectype) / 2) + || insn_code == CODE_FOR_nothing) + return false; + + /* We can use the optimized pattern. */ if (in0 == NULL_RTX && in1 == NULL_RTX) - { - wide_int val = wi::add (cst, 1); - int pow = wi::exact_log2 (val); - return pow == (int)(element_precision (vectype) / 2); - } + return true; if (!VECTOR_TYPE_P (vectype)) return false; diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/pr107830-1.c b/gcc/testsuite/gcc.target/aarch64/sve2/pr107830-1.c new file mode 100644 index 00000000000..6d8ee3615fd --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve2/pr107830-1.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target fopenmp } */ +/* { dg-additional-options "-Os -fopenmp" } */ + +void +f2 (int *a) +{ + unsigned int i; + +#pragma omp simd + for (i = 0; i < 4; ++i) + a[i / 3] -= 4; +} diff --git a/gcc/testsuite/gcc.target/aarch64/sve2/pr107830-2.c b/gcc/testsuite/gcc.target/aarch64/sve2/pr107830-2.c new file mode 100644 index 00000000000..4ec45d7a47e --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve2/pr107830-2.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-additional-options "-O3 -msve-vector-bits=512" } */ + +void f(unsigned short *restrict p1, unsigned int *restrict p2) +{ + for (int i = 0; i < 16; ++i) + { + p1[i] /= 0xff; + p2[i] += 1; + } +} +
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