From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 2092) id 68FB6385B1A5; Mon, 28 Nov 2022 09:11:29 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 68FB6385B1A5 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1669626689; bh=/qmdPyzUmmMUcdt5cab3ETlgpTpGbqkdwmqkrS/MItM=; h=From:To:Subject:Date:From; b=KkIcnoW9UyNU6LN8HuHF4YFNC8fbWuytuMYrabeTgnf1asoKLpktNl2xW13GEdUQ9 eXyIVUQGSWrdWAASuSgI1ApmpsWzhjNZ/wkj2J++ASo9vHmL+DjRfhI9SzJ1ACmbRd 9z7xhAbKJaDylqg+IFS0z/xoRRE4n1Q2QZAcg+Mc= MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="utf-8" From: Andrea Corallo To: gcc-cvs@gcc.gnu.org Subject: [gcc r13-4325] arm: improve tests for vmin* X-Act-Checkin: gcc X-Git-Author: Andrea Corallo X-Git-Refname: refs/heads/trunk X-Git-Oldrev: 1fa5a44736062eeccd241ebeb1771bd77b7fd168 X-Git-Newrev: d117647edc8fcae63abbdecbf38e9f22d0b1e3de Message-Id: <20221128091129.68FB6385B1A5@sourceware.org> Date: Mon, 28 Nov 2022 09:11:29 +0000 (GMT) List-Id: https://gcc.gnu.org/g:d117647edc8fcae63abbdecbf38e9f22d0b1e3de commit r13-4325-gd117647edc8fcae63abbdecbf38e9f22d0b1e3de Author: Andrea Corallo Date: Mon Oct 10 16:21:40 2022 +0200 arm: improve tests for vmin* gcc/testsuite/ChangeLog: * gcc.target/arm/mve/intrinsics/vminaq_m_s16.c: Improve test. * gcc.target/arm/mve/intrinsics/vminaq_m_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vminaq_m_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vminaq_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vminaq_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vminaq_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vminavq_p_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vminavq_p_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vminavq_p_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vminavq_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vminavq_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vminavq_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vminnmaq_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vminnmaq_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vminnmaq_m_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vminnmaq_m_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vminnmavq_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vminnmavq_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vminnmavq_p_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vminnmavq_p_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vminnmq_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vminnmq_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vminnmq_m_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vminnmq_m_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vminnmq_x_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vminnmq_x_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vminnmvq_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vminnmvq_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vminnmvq_p_f16.c: Likewise. * gcc.target/arm/mve/intrinsics/vminnmvq_p_f32.c: Likewise. * gcc.target/arm/mve/intrinsics/vminq_m_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vminq_m_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vminq_m_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vminq_m_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vminq_m_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vminq_m_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vminq_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vminq_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vminq_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vminq_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vminq_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vminq_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vminq_x_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vminq_x_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vminq_x_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vminq_x_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vminq_x_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vminq_x_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vminvq_p_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vminvq_p_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vminvq_p_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vminvq_p_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vminvq_p_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vminvq_p_u8.c: Likewise. * gcc.target/arm/mve/intrinsics/vminvq_s16.c: Likewise. * gcc.target/arm/mve/intrinsics/vminvq_s32.c: Likewise. * gcc.target/arm/mve/intrinsics/vminvq_s8.c: Likewise. * gcc.target/arm/mve/intrinsics/vminvq_u16.c: Likewise. * gcc.target/arm/mve/intrinsics/vminvq_u32.c: Likewise. * gcc.target/arm/mve/intrinsics/vminvq_u8.c: Likewise. Diff: --- .../gcc.target/arm/mve/intrinsics/vminaq_m_s16.c | 25 +++++++++++-- .../gcc.target/arm/mve/intrinsics/vminaq_m_s32.c | 25 +++++++++++-- .../gcc.target/arm/mve/intrinsics/vminaq_m_s8.c | 25 +++++++++++-- .../gcc.target/arm/mve/intrinsics/vminaq_s16.c | 16 +++++++-- .../gcc.target/arm/mve/intrinsics/vminaq_s32.c | 16 +++++++-- .../gcc.target/arm/mve/intrinsics/vminaq_s8.c | 16 +++++++-- .../gcc.target/arm/mve/intrinsics/vminavq_p_s16.c | 41 ++++++++++++++++++---- .../gcc.target/arm/mve/intrinsics/vminavq_p_s32.c | 41 ++++++++++++++++++---- .../gcc.target/arm/mve/intrinsics/vminavq_p_s8.c | 41 ++++++++++++++++++---- .../gcc.target/arm/mve/intrinsics/vminavq_s16.c | 29 +++++++++++---- .../gcc.target/arm/mve/intrinsics/vminavq_s32.c | 29 +++++++++++---- .../gcc.target/arm/mve/intrinsics/vminavq_s8.c | 29 +++++++++++---- .../gcc.target/arm/mve/intrinsics/vminnmaq_f16.c | 16 +++++++-- .../gcc.target/arm/mve/intrinsics/vminnmaq_f32.c | 16 +++++++-- .../gcc.target/arm/mve/intrinsics/vminnmaq_m_f16.c | 25 +++++++++++-- .../gcc.target/arm/mve/intrinsics/vminnmaq_m_f32.c | 25 +++++++++++-- .../gcc.target/arm/mve/intrinsics/vminnmavq_f16.c | 27 +++++++++++--- .../gcc.target/arm/mve/intrinsics/vminnmavq_f32.c | 27 +++++++++++--- .../arm/mve/intrinsics/vminnmavq_p_f16.c | 39 +++++++++++++++++--- .../arm/mve/intrinsics/vminnmavq_p_f32.c | 39 +++++++++++++++++--- .../gcc.target/arm/mve/intrinsics/vminnmq_f16.c | 16 +++++++-- .../gcc.target/arm/mve/intrinsics/vminnmq_f32.c | 16 +++++++-- .../gcc.target/arm/mve/intrinsics/vminnmq_m_f16.c | 26 +++++++++++--- .../gcc.target/arm/mve/intrinsics/vminnmq_m_f32.c | 26 +++++++++++--- .../gcc.target/arm/mve/intrinsics/vminnmq_x_f16.c | 25 +++++++++++-- .../gcc.target/arm/mve/intrinsics/vminnmq_x_f32.c | 25 +++++++++++-- .../gcc.target/arm/mve/intrinsics/vminnmvq_f16.c | 27 +++++++++++--- .../gcc.target/arm/mve/intrinsics/vminnmvq_f32.c | 27 +++++++++++--- .../gcc.target/arm/mve/intrinsics/vminnmvq_p_f16.c | 39 +++++++++++++++++--- .../gcc.target/arm/mve/intrinsics/vminnmvq_p_f32.c | 39 +++++++++++++++++--- .../gcc.target/arm/mve/intrinsics/vminq_m_s16.c | 26 +++++++++++--- .../gcc.target/arm/mve/intrinsics/vminq_m_s32.c | 26 +++++++++++--- .../gcc.target/arm/mve/intrinsics/vminq_m_s8.c | 26 +++++++++++--- .../gcc.target/arm/mve/intrinsics/vminq_m_u16.c | 26 +++++++++++--- .../gcc.target/arm/mve/intrinsics/vminq_m_u32.c | 26 +++++++++++--- .../gcc.target/arm/mve/intrinsics/vminq_m_u8.c | 26 +++++++++++--- .../gcc.target/arm/mve/intrinsics/vminq_s16.c | 16 +++++++-- .../gcc.target/arm/mve/intrinsics/vminq_s32.c | 16 +++++++-- .../gcc.target/arm/mve/intrinsics/vminq_s8.c | 16 +++++++-- .../gcc.target/arm/mve/intrinsics/vminq_u16.c | 16 +++++++-- .../gcc.target/arm/mve/intrinsics/vminq_u32.c | 16 +++++++-- .../gcc.target/arm/mve/intrinsics/vminq_u8.c | 16 +++++++-- .../gcc.target/arm/mve/intrinsics/vminq_x_s16.c | 25 +++++++++++-- .../gcc.target/arm/mve/intrinsics/vminq_x_s32.c | 25 +++++++++++-- .../gcc.target/arm/mve/intrinsics/vminq_x_s8.c | 25 +++++++++++-- .../gcc.target/arm/mve/intrinsics/vminq_x_u16.c | 25 +++++++++++-- .../gcc.target/arm/mve/intrinsics/vminq_x_u32.c | 25 +++++++++++-- .../gcc.target/arm/mve/intrinsics/vminq_x_u8.c | 25 +++++++++++-- .../gcc.target/arm/mve/intrinsics/vminvq_p_s16.c | 31 +++++++++++----- .../gcc.target/arm/mve/intrinsics/vminvq_p_s32.c | 31 +++++++++++----- .../gcc.target/arm/mve/intrinsics/vminvq_p_s8.c | 31 +++++++++++----- .../gcc.target/arm/mve/intrinsics/vminvq_p_u16.c | 39 +++++++++++++++++--- .../gcc.target/arm/mve/intrinsics/vminvq_p_u32.c | 39 +++++++++++++++++--- .../gcc.target/arm/mve/intrinsics/vminvq_p_u8.c | 39 +++++++++++++++++--- .../gcc.target/arm/mve/intrinsics/vminvq_s16.c | 22 +++++++----- .../gcc.target/arm/mve/intrinsics/vminvq_s32.c | 22 +++++++----- .../gcc.target/arm/mve/intrinsics/vminvq_s8.c | 22 +++++++----- .../gcc.target/arm/mve/intrinsics/vminvq_u16.c | 29 +++++++++++---- .../gcc.target/arm/mve/intrinsics/vminvq_u32.c | 26 +++++++++++--- .../gcc.target/arm/mve/intrinsics/vminvq_u8.c | 29 +++++++++++---- 60 files changed, 1320 insertions(+), 255 deletions(-) diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminaq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminaq_m_s16.c index 0324110c6a8..925b9154ca7 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminaq_m_s16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminaq_m_s16.c @@ -1,22 +1,41 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vminat.s16 q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ uint16x8_t foo (uint16x8_t a, int16x8_t b, mve_pred16_t p) { return vminaq_m_s16 (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vminat.s16" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vminat.s16 q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ uint16x8_t foo1 (uint16x8_t a, int16x8_t b, mve_pred16_t p) { return vminaq_m (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminaq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminaq_m_s32.c index a2886d4f40f..296f69dfcda 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminaq_m_s32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminaq_m_s32.c @@ -1,22 +1,41 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vminat.s32 q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ uint32x4_t foo (uint32x4_t a, int32x4_t b, mve_pred16_t p) { return vminaq_m_s32 (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vminat.s32" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vminat.s32 q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ uint32x4_t foo1 (uint32x4_t a, int32x4_t b, mve_pred16_t p) { return vminaq_m (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminaq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminaq_m_s8.c index 95eb038efc0..cf6fecc3461 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminaq_m_s8.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminaq_m_s8.c @@ -1,22 +1,41 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vminat.s8 q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ uint8x16_t foo (uint8x16_t a, int8x16_t b, mve_pred16_t p) { return vminaq_m_s8 (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vminat.s8" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vminat.s8 q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ uint8x16_t foo1 (uint8x16_t a, int8x16_t b, mve_pred16_t p) { return vminaq_m (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminaq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminaq_s16.c index 3a157e00a27..63f59f8c80a 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminaq_s16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminaq_s16.c @@ -1,21 +1,33 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmina.s16 q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ uint16x8_t foo (uint16x8_t a, int16x8_t b) { return vminaq_s16 (a, b); } -/* { dg-final { scan-assembler "vmina.s16" } } */ +/* +**foo1: +** ... +** vmina.s16 q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ uint16x8_t foo1 (uint16x8_t a, int16x8_t b) { return vminaq (a, b); } -/* { dg-final { scan-assembler "vmina.s16" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminaq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminaq_s32.c index 5c732c65d63..eb0a54cbe19 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminaq_s32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminaq_s32.c @@ -1,21 +1,33 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmina.s32 q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ uint32x4_t foo (uint32x4_t a, int32x4_t b) { return vminaq_s32 (a, b); } -/* { dg-final { scan-assembler "vmina.s32" } } */ +/* +**foo1: +** ... +** vmina.s32 q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ uint32x4_t foo1 (uint32x4_t a, int32x4_t b) { return vminaq (a, b); } -/* { dg-final { scan-assembler "vmina.s32" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminaq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminaq_s8.c index 2e4dad141ce..b875308863d 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminaq_s8.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminaq_s8.c @@ -1,21 +1,33 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmina.s8 q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ uint8x16_t foo (uint8x16_t a, int8x16_t b) { return vminaq_s8 (a, b); } -/* { dg-final { scan-assembler "vmina.s8" } } */ +/* +**foo1: +** ... +** vmina.s8 q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ uint8x16_t foo1 (uint8x16_t a, int8x16_t b) { return vminaq (a, b); } -/* { dg-final { scan-assembler "vmina.s8" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminavq_p_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminavq_p_s16.c index 9303ae02e39..5d3c40fb1fc 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminavq_p_s16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminavq_p_s16.c @@ -1,9 +1,20 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vminavt.s16 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) +** ... +*/ uint16_t foo (uint16_t a, int16x8_t b, mve_pred16_t p) { @@ -11,18 +22,36 @@ foo (uint16_t a, int16x8_t b, mve_pred16_t p) } +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vminavt.s16 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) +** ... +*/ uint16_t foo1 (uint16_t a, int16x8_t b, mve_pred16_t p) { return vminavq_p (a, b, p); } - -int16_t -foo2 (uint8_t a, int16x8_t b, mve_pred16_t p) +/* +**foo2: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vminavt.s16 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) +** ... +*/ +uint16_t +foo2 (int16x8_t b, mve_pred16_t p) { - return vminavq_p (a, b, p); + return vminavq_p (1, b, p); } -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ -/* { dg-final { scan-assembler-times "vminavt.s16" 3 } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminavq_p_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminavq_p_s32.c index 36247f68b2c..ee4ff251d63 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminavq_p_s32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminavq_p_s32.c @@ -1,9 +1,20 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vminavt.s32 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) +** ... +*/ uint32_t foo (uint32_t a, int32x4_t b, mve_pred16_t p) { @@ -11,18 +22,36 @@ foo (uint32_t a, int32x4_t b, mve_pred16_t p) } +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vminavt.s32 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) +** ... +*/ uint32_t foo1 (uint32_t a, int32x4_t b, mve_pred16_t p) { return vminavq_p (a, b, p); } - -int32_t -foo2 (uint16_t a, int32x4_t b, mve_pred16_t p) +/* +**foo2: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vminavt.s32 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) +** ... +*/ +uint32_t +foo2 (int32x4_t b, mve_pred16_t p) { - return vminavq_p (a, b, p); + return vminavq_p (1, b, p); } -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ -/* { dg-final { scan-assembler-times "vminavt.s32" 3 } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminavq_p_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminavq_p_s8.c index d3361615dcc..14602c29719 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminavq_p_s8.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminavq_p_s8.c @@ -1,9 +1,20 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vminavt.s8 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) +** ... +*/ uint8_t foo (uint8_t a, int8x16_t b, mve_pred16_t p) { @@ -11,18 +22,36 @@ foo (uint8_t a, int8x16_t b, mve_pred16_t p) } +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vminavt.s8 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) +** ... +*/ uint8_t foo1 (uint8_t a, int8x16_t b, mve_pred16_t p) { return vminavq_p (a, b, p); } - -int8_t -foo2 (uint32_t a, int8x16_t b, mve_pred16_t p) +/* +**foo2: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vminavt.s8 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) +** ... +*/ +uint8_t +foo2 (int8x16_t b, mve_pred16_t p) { - return vminavq_p (a, b, p); + return vminavq_p (1, b, p); } -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ -/* { dg-final { scan-assembler-times "vminavt.s8" 3 } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminavq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminavq_s16.c index 17e4edca2f1..51f75ae1f6a 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminavq_s16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminavq_s16.c @@ -1,9 +1,16 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vminav.s16 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) +** ... +*/ uint16_t foo (uint16_t a, int16x8_t b) { @@ -11,18 +18,28 @@ foo (uint16_t a, int16x8_t b) } +/* +**foo1: +** ... +** vminav.s16 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) +** ... +*/ uint16_t foo1 (uint16_t a, int16x8_t b) { return vminavq (a, b); } - -int16_t -foo2 (uint8_t a, int16x8_t b) +/* +**foo2: +** ... +** vminav.s16 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) +** ... +*/ +uint16_t +foo2 (int16x8_t b) { - return vminavq (a, b); + return vminavq (1, b); } -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ -/* { dg-final { scan-assembler-times "vminav.s16" 3 } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminavq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminavq_s32.c index 032d02b8857..d1602cebe18 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminavq_s32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminavq_s32.c @@ -1,9 +1,16 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vminav.s32 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) +** ... +*/ uint32_t foo (uint32_t a, int32x4_t b) { @@ -11,18 +18,28 @@ foo (uint32_t a, int32x4_t b) } +/* +**foo1: +** ... +** vminav.s32 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) +** ... +*/ uint32_t foo1 (uint32_t a, int32x4_t b) { return vminavq (a, b); } - -int32_t -foo2 (uint16_t a, int32x4_t b) +/* +**foo2: +** ... +** vminav.s32 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) +** ... +*/ +uint32_t +foo2 (int32x4_t b) { - return vminavq (a, b); + return vminavq (1, b); } -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ -/* { dg-final { scan-assembler-times "vminav.s32" 3 } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminavq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminavq_s8.c index 2a2bb3d6146..f4c9b045b90 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminavq_s8.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminavq_s8.c @@ -1,9 +1,16 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vminav.s8 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) +** ... +*/ uint8_t foo (uint8_t a, int8x16_t b) { @@ -11,18 +18,28 @@ foo (uint8_t a, int8x16_t b) } +/* +**foo1: +** ... +** vminav.s8 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) +** ... +*/ uint8_t foo1 (uint8_t a, int8x16_t b) { return vminavq (a, b); } - -int8_t -foo2 (uint32_t a, int8x16_t b) +/* +**foo2: +** ... +** vminav.s8 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) +** ... +*/ +uint8_t +foo2 (int8x16_t b) { - return vminavq (a, b); + return vminavq (1, b); } -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ -/* { dg-final { scan-assembler-times "vminav.s8" 3 } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmaq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmaq_f16.c index cf32186d642..1728d104266 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmaq_f16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmaq_f16.c @@ -1,21 +1,33 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vminnma.f16 q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ float16x8_t foo (float16x8_t a, float16x8_t b) { return vminnmaq_f16 (a, b); } -/* { dg-final { scan-assembler "vminnma.f16" } } */ +/* +**foo1: +** ... +** vminnma.f16 q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ float16x8_t foo1 (float16x8_t a, float16x8_t b) { return vminnmaq (a, b); } -/* { dg-final { scan-assembler "vminnma.f16" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmaq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmaq_f32.c index 1c3f19c9e1b..42b4265d9cc 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmaq_f32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmaq_f32.c @@ -1,21 +1,33 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vminnma.f32 q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ float32x4_t foo (float32x4_t a, float32x4_t b) { return vminnmaq_f32 (a, b); } -/* { dg-final { scan-assembler "vminnma.f32" } } */ +/* +**foo1: +** ... +** vminnma.f32 q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ float32x4_t foo1 (float32x4_t a, float32x4_t b) { return vminnmaq (a, b); } -/* { dg-final { scan-assembler "vminnma.f32" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmaq_m_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmaq_m_f16.c index 4423903e913..51b85bd2b04 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmaq_m_f16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmaq_m_f16.c @@ -1,22 +1,41 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vminnmat.f16 q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ float16x8_t foo (float16x8_t a, float16x8_t b, mve_pred16_t p) { return vminnmaq_m_f16 (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vminnmat.f16" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vminnmat.f16 q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ float16x8_t foo1 (float16x8_t a, float16x8_t b, mve_pred16_t p) { return vminnmaq_m (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmaq_m_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmaq_m_f32.c index 683f40ad3d8..2f0423ecb4f 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmaq_m_f32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmaq_m_f32.c @@ -1,22 +1,41 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vminnmat.f32 q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ float32x4_t foo (float32x4_t a, float32x4_t b, mve_pred16_t p) { return vminnmaq_m_f32 (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vminnmat.f32" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vminnmat.f32 q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ float32x4_t foo1 (float32x4_t a, float32x4_t b, mve_pred16_t p) { return vminnmaq_m (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmavq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmavq_f16.c index fadb23e05c8..17e4ad16759 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmavq_f16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmavq_f16.c @@ -1,9 +1,16 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vminnmav.f16 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) +** ... +*/ float16_t foo (float16_t a, float16x8_t b) { @@ -11,18 +18,28 @@ foo (float16_t a, float16x8_t b) } +/* +**foo1: +** ... +** vminnmav.f16 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) +** ... +*/ float16_t foo1 (float16_t a, float16x8_t b) { return vminnmavq (a, b); } - +/* +**foo2: +** ... +** vminnmav.f16 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) +** ... +*/ float16_t -foo2 (float32_t a, float16x8_t b) +foo2 (float16x8_t b) { - return vminnmavq (a, b); + return vminnmavq (1.1, b); } -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ -/* { dg-final { scan-assembler-times "vminnmav.f16" 3 } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmavq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmavq_f32.c index 84714a96b9f..2758e59666e 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmavq_f32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmavq_f32.c @@ -1,9 +1,16 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vminnmav.f32 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) +** ... +*/ float32_t foo (float32_t a, float32x4_t b) { @@ -11,18 +18,28 @@ foo (float32_t a, float32x4_t b) } +/* +**foo1: +** ... +** vminnmav.f32 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) +** ... +*/ float32_t foo1 (float32_t a, float32x4_t b) { return vminnmavq (a, b); } - +/* +**foo2: +** ... +** vminnmav.f32 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) +** ... +*/ float32_t -foo2 (float16_t a, float32x4_t b) +foo2 (float32x4_t b) { - return vminnmavq (a, b); + return vminnmavq (1.1, b); } -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ -/* { dg-final { scan-assembler-times "vminnmav.f32" 3 } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmavq_p_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmavq_p_f16.c index c79fa307ae0..b60a6627aea 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmavq_p_f16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmavq_p_f16.c @@ -1,9 +1,20 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vminnmavt.f16 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) +** ... +*/ float16_t foo (float16_t a, float16x8_t b, mve_pred16_t p) { @@ -11,18 +22,36 @@ foo (float16_t a, float16x8_t b, mve_pred16_t p) } +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vminnmavt.f16 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) +** ... +*/ float16_t foo1 (float16_t a, float16x8_t b, mve_pred16_t p) { return vminnmavq_p (a, b, p); } - +/* +**foo2: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vminnmavt.f16 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) +** ... +*/ float16_t -foo2 (float32_t a, float16x8_t b, mve_pred16_t p) +foo2 (float16x8_t b, mve_pred16_t p) { - return vminnmavq_p (a, b, p); + return vminnmavq_p (1.1, b, p); } -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ -/* { dg-final { scan-assembler-times "vminnmavt.f16" 3 } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmavq_p_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmavq_p_f32.c index bea04c7aac6..6fa97b74a65 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmavq_p_f32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmavq_p_f32.c @@ -1,9 +1,20 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vminnmavt.f32 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) +** ... +*/ float32_t foo (float32_t a, float32x4_t b, mve_pred16_t p) { @@ -11,18 +22,36 @@ foo (float32_t a, float32x4_t b, mve_pred16_t p) } +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vminnmavt.f32 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) +** ... +*/ float32_t foo1 (float32_t a, float32x4_t b, mve_pred16_t p) { return vminnmavq_p (a, b, p); } - +/* +**foo2: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vminnmavt.f32 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) +** ... +*/ float32_t -foo2 (float16_t a, float32x4_t b, mve_pred16_t p) +foo2 (float32x4_t b, mve_pred16_t p) { - return vminnmavq_p (a, b, p); + return vminnmavq_p (1.1, b, p); } -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ -/* { dg-final { scan-assembler-times "vminnmavt.f32" 3 } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmq_f16.c index 18d4a4c1330..c0962b52631 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmq_f16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmq_f16.c @@ -1,21 +1,33 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vminnm.f16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ float16x8_t foo (float16x8_t a, float16x8_t b) { return vminnmq_f16 (a, b); } -/* { dg-final { scan-assembler "vminnm.f16" } } */ +/* +**foo1: +** ... +** vminnm.f16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ float16x8_t foo1 (float16x8_t a, float16x8_t b) { return vminnmq (a, b); } -/* { dg-final { scan-assembler "vminnm.f16" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmq_f32.c index 34144cad17f..a9c3e5f74b1 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmq_f32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmq_f32.c @@ -1,21 +1,33 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vminnm.f32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ float32x4_t foo (float32x4_t a, float32x4_t b) { return vminnmq_f32 (a, b); } -/* { dg-final { scan-assembler "vminnm.f32" } } */ +/* +**foo1: +** ... +** vminnm.f32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ float32x4_t foo1 (float32x4_t a, float32x4_t b) { return vminnmq (a, b); } -/* { dg-final { scan-assembler "vminnm.f32" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmq_m_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmq_m_f16.c index e5533d28035..466264249c5 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmq_m_f16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmq_m_f16.c @@ -1,23 +1,41 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vminnmt.f16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ float16x8_t foo (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p) { return vminnmq_m_f16 (inactive, a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vminnmt.f16" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vminnmt.f16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ float16x8_t foo1 (float16x8_t inactive, float16x8_t a, float16x8_t b, mve_pred16_t p) { return vminnmq_m (inactive, a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vminnmt.f16" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmq_m_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmq_m_f32.c index 382d16c4489..57edc8e1a80 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmq_m_f32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmq_m_f32.c @@ -1,23 +1,41 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vminnmt.f32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ float32x4_t foo (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p) { return vminnmq_m_f32 (inactive, a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vminnmt.f32" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vminnmt.f32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ float32x4_t foo1 (float32x4_t inactive, float32x4_t a, float32x4_t b, mve_pred16_t p) { return vminnmq_m (inactive, a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vminnmt.f32" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmq_x_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmq_x_f16.c index 04d606ce5cd..73b4ccba080 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmq_x_f16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmq_x_f16.c @@ -1,22 +1,41 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vminnmt.f16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ float16x8_t foo (float16x8_t a, float16x8_t b, mve_pred16_t p) { return vminnmq_x_f16 (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vminnmt.f16" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vminnmt.f16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ float16x8_t foo1 (float16x8_t a, float16x8_t b, mve_pred16_t p) { return vminnmq_x (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmq_x_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmq_x_f32.c index 87cd970fd11..9a824566212 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmq_x_f32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmq_x_f32.c @@ -1,22 +1,41 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vminnmt.f32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ float32x4_t foo (float32x4_t a, float32x4_t b, mve_pred16_t p) { return vminnmq_x_f32 (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vminnmt.f32" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vminnmt.f32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ float32x4_t foo1 (float32x4_t a, float32x4_t b, mve_pred16_t p) { return vminnmq_x (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmvq_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmvq_f16.c index 0eb3a4af14e..dc00d02df7d 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmvq_f16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmvq_f16.c @@ -1,9 +1,16 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vminnmv.f16 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) +** ... +*/ float16_t foo (float16_t a, float16x8_t b) { @@ -11,18 +18,28 @@ foo (float16_t a, float16x8_t b) } +/* +**foo1: +** ... +** vminnmv.f16 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) +** ... +*/ float16_t foo1 (float16_t a, float16x8_t b) { return vminnmvq (a, b); } - +/* +**foo2: +** ... +** vminnmv.f16 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) +** ... +*/ float16_t -foo2 (float32_t a, float16x8_t b) +foo2 (float16x8_t b) { - return vminnmvq (a, b); + return vminnmvq (1.1, b); } -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ -/* { dg-final { scan-assembler-times "vminnmv.f16" 3 } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmvq_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmvq_f32.c index f3183508f8e..ff23c818452 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmvq_f32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmvq_f32.c @@ -1,9 +1,16 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vminnmv.f32 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) +** ... +*/ float32_t foo (float32_t a, float32x4_t b) { @@ -11,18 +18,28 @@ foo (float32_t a, float32x4_t b) } +/* +**foo1: +** ... +** vminnmv.f32 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) +** ... +*/ float32_t foo1 (float32_t a, float32x4_t b) { return vminnmvq (a, b); } - +/* +**foo2: +** ... +** vminnmv.f32 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) +** ... +*/ float32_t -foo2 (float16_t a, float32x4_t b) +foo2 (float32x4_t b) { - return vminnmvq (a, b); + return vminnmvq (1.1, b); } -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ -/* { dg-final { scan-assembler-times "vminnmv.f32" 3 } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmvq_p_f16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmvq_p_f16.c index 16f6ac514c8..ad99f586d11 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmvq_p_f16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmvq_p_f16.c @@ -1,9 +1,20 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vminnmvt.f16 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) +** ... +*/ float16_t foo (float16_t a, float16x8_t b, mve_pred16_t p) { @@ -11,18 +22,36 @@ foo (float16_t a, float16x8_t b, mve_pred16_t p) } +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vminnmvt.f16 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) +** ... +*/ float16_t foo1 (float16_t a, float16x8_t b, mve_pred16_t p) { return vminnmvq_p (a, b, p); } - +/* +**foo2: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vminnmvt.f16 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) +** ... +*/ float16_t -foo2 (float32_t a, float16x8_t b, mve_pred16_t p) +foo2 (float16x8_t b, mve_pred16_t p) { - return vminnmvq_p (a, b, p); + return vminnmvq_p (1.1, b, p); } -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ -/* { dg-final { scan-assembler-times "vminnmvt.f16" 3 } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmvq_p_f32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmvq_p_f32.c index a8e4f9ffba7..3c7e5c07a68 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmvq_p_f32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminnmvq_p_f32.c @@ -1,9 +1,20 @@ /* { dg-require-effective-target arm_v8_1m_mve_fp_ok } */ /* { dg-add-options arm_v8_1m_mve_fp } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vminnmvt.f32 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) +** ... +*/ float32_t foo (float32_t a, float32x4_t b, mve_pred16_t p) { @@ -11,18 +22,36 @@ foo (float32_t a, float32x4_t b, mve_pred16_t p) } +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vminnmvt.f32 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) +** ... +*/ float32_t foo1 (float32_t a, float32x4_t b, mve_pred16_t p) { return vminnmvq_p (a, b, p); } - +/* +**foo2: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vminnmvt.f32 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) +** ... +*/ float32_t -foo2 (float16_t a, float32x4_t b, mve_pred16_t p) +foo2 (float32x4_t b, mve_pred16_t p) { - return vminnmvq_p (a, b, p); + return vminnmvq_p (1.1, b, p); } -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ -/* { dg-final { scan-assembler-times "vminnmvt.f32" 3 } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_m_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_m_s16.c index f257ddcf600..fe7368eeb38 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_m_s16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_m_s16.c @@ -1,23 +1,41 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vmint.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ int16x8_t foo (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p) { return vminq_m_s16 (inactive, a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vmint.s16" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vmint.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ int16x8_t foo1 (int16x8_t inactive, int16x8_t a, int16x8_t b, mve_pred16_t p) { return vminq_m (inactive, a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vmint.s16" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_m_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_m_s32.c index 957da71d0e3..a90a1db8835 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_m_s32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_m_s32.c @@ -1,23 +1,41 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vmint.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ int32x4_t foo (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p) { return vminq_m_s32 (inactive, a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vmint.s32" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vmint.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ int32x4_t foo1 (int32x4_t inactive, int32x4_t a, int32x4_t b, mve_pred16_t p) { return vminq_m (inactive, a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vmint.s32" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_m_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_m_s8.c index fea8bfd7994..911bd3af0dc 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_m_s8.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_m_s8.c @@ -1,23 +1,41 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vmint.s8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ int8x16_t foo (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p) { return vminq_m_s8 (inactive, a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vmint.s8" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vmint.s8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ int8x16_t foo1 (int8x16_t inactive, int8x16_t a, int8x16_t b, mve_pred16_t p) { return vminq_m (inactive, a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vmint.s8" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_m_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_m_u16.c index 7cc19a7dd5d..f80288aaf79 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_m_u16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_m_u16.c @@ -1,23 +1,41 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vmint.u16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ uint16x8_t foo (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p) { return vminq_m_u16 (inactive, a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vmint.u16" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vmint.u16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ uint16x8_t foo1 (uint16x8_t inactive, uint16x8_t a, uint16x8_t b, mve_pred16_t p) { return vminq_m (inactive, a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vmint.u16" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_m_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_m_u32.c index 301fbfc751f..b480089f4f3 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_m_u32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_m_u32.c @@ -1,23 +1,41 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vmint.u32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ uint32x4_t foo (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p) { return vminq_m_u32 (inactive, a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vmint.u32" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vmint.u32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ uint32x4_t foo1 (uint32x4_t inactive, uint32x4_t a, uint32x4_t b, mve_pred16_t p) { return vminq_m (inactive, a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vmint.u32" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_m_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_m_u8.c index 7a65b3557a3..73633c9612e 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_m_u8.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_m_u8.c @@ -1,23 +1,41 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vmint.u8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ uint8x16_t foo (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p) { return vminq_m_u8 (inactive, a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vmint.u8" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vmint.u8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ uint8x16_t foo1 (uint8x16_t inactive, uint8x16_t a, uint8x16_t b, mve_pred16_t p) { return vminq_m (inactive, a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vmint.u8" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_s16.c index d46a3c4ee18..eb34dc4c41c 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_s16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_s16.c @@ -1,21 +1,33 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmin.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ int16x8_t foo (int16x8_t a, int16x8_t b) { return vminq_s16 (a, b); } -/* { dg-final { scan-assembler "vmin.s16" } } */ +/* +**foo1: +** ... +** vmin.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ int16x8_t foo1 (int16x8_t a, int16x8_t b) { return vminq (a, b); } -/* { dg-final { scan-assembler "vmin.s16" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_s32.c index 601e918a5bf..60d29da4e14 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_s32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_s32.c @@ -1,21 +1,33 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmin.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ int32x4_t foo (int32x4_t a, int32x4_t b) { return vminq_s32 (a, b); } -/* { dg-final { scan-assembler "vmin.s32" } } */ +/* +**foo1: +** ... +** vmin.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ int32x4_t foo1 (int32x4_t a, int32x4_t b) { return vminq (a, b); } -/* { dg-final { scan-assembler "vmin.s32" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_s8.c index e2ae2341ad8..675fb8edfb1 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_s8.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_s8.c @@ -1,21 +1,33 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmin.s8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ int8x16_t foo (int8x16_t a, int8x16_t b) { return vminq_s8 (a, b); } -/* { dg-final { scan-assembler "vmin.s8" } } */ +/* +**foo1: +** ... +** vmin.s8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ int8x16_t foo1 (int8x16_t a, int8x16_t b) { return vminq (a, b); } -/* { dg-final { scan-assembler "vmin.s8" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_u16.c index 3cac573f6ef..50f648d5133 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_u16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_u16.c @@ -1,21 +1,33 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmin.u16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ uint16x8_t foo (uint16x8_t a, uint16x8_t b) { return vminq_u16 (a, b); } -/* { dg-final { scan-assembler "vmin.u16" } } */ +/* +**foo1: +** ... +** vmin.u16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ uint16x8_t foo1 (uint16x8_t a, uint16x8_t b) { return vminq (a, b); } -/* { dg-final { scan-assembler "vmin.u16" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_u32.c index ca3ef245fe9..bcfead39c5a 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_u32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_u32.c @@ -1,21 +1,33 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmin.u32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ uint32x4_t foo (uint32x4_t a, uint32x4_t b) { return vminq_u32 (a, b); } -/* { dg-final { scan-assembler "vmin.u32" } } */ +/* +**foo1: +** ... +** vmin.u32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ uint32x4_t foo1 (uint32x4_t a, uint32x4_t b) { return vminq (a, b); } -/* { dg-final { scan-assembler "vmin.u32" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_u8.c index b7ef4db22ff..e8eacae4da8 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_u8.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_u8.c @@ -1,21 +1,33 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmin.u8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ uint8x16_t foo (uint8x16_t a, uint8x16_t b) { return vminq_u8 (a, b); } -/* { dg-final { scan-assembler "vmin.u8" } } */ +/* +**foo1: +** ... +** vmin.u8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ uint8x16_t foo1 (uint8x16_t a, uint8x16_t b) { return vminq (a, b); } -/* { dg-final { scan-assembler "vmin.u8" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_x_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_x_s16.c index af93c78658e..0d8987e16b8 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_x_s16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_x_s16.c @@ -1,22 +1,41 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vmint.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ int16x8_t foo (int16x8_t a, int16x8_t b, mve_pred16_t p) { return vminq_x_s16 (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vmint.s16" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vmint.s16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ int16x8_t foo1 (int16x8_t a, int16x8_t b, mve_pred16_t p) { return vminq_x (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_x_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_x_s32.c index 76f0831e48e..3c3595171ea 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_x_s32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_x_s32.c @@ -1,22 +1,41 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vmint.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ int32x4_t foo (int32x4_t a, int32x4_t b, mve_pred16_t p) { return vminq_x_s32 (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vmint.s32" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vmint.s32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ int32x4_t foo1 (int32x4_t a, int32x4_t b, mve_pred16_t p) { return vminq_x (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_x_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_x_s8.c index fdd6e94497c..402c4aa121d 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_x_s8.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_x_s8.c @@ -1,22 +1,41 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vmint.s8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ int8x16_t foo (int8x16_t a, int8x16_t b, mve_pred16_t p) { return vminq_x_s8 (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vmint.s8" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vmint.s8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ int8x16_t foo1 (int8x16_t a, int8x16_t b, mve_pred16_t p) { return vminq_x (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_x_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_x_u16.c index 9842954c761..e27a3416e38 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_x_u16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_x_u16.c @@ -1,22 +1,41 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vmint.u16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ uint16x8_t foo (uint16x8_t a, uint16x8_t b, mve_pred16_t p) { return vminq_x_u16 (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vmint.u16" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vmint.u16 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ uint16x8_t foo1 (uint16x8_t a, uint16x8_t b, mve_pred16_t p) { return vminq_x (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_x_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_x_u32.c index 741e4508879..d3cb29bf60c 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_x_u32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_x_u32.c @@ -1,22 +1,41 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vmint.u32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ uint32x4_t foo (uint32x4_t a, uint32x4_t b, mve_pred16_t p) { return vminq_x_u32 (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vmint.u32" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vmint.u32 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ uint32x4_t foo1 (uint32x4_t a, uint32x4_t b, mve_pred16_t p) { return vminq_x (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_x_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_x_u8.c index 13743fc87a1..3e05ef7dd13 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_x_u8.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminq_x_u8.c @@ -1,22 +1,41 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vmint.u8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ uint8x16_t foo (uint8x16_t a, uint8x16_t b, mve_pred16_t p) { return vminq_x_u8 (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ -/* { dg-final { scan-assembler "vmint.u8" } } */ +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vmint.u8 q[0-9]+, q[0-9]+, q[0-9]+(?: @.*|) +** ... +*/ uint8x16_t foo1 (uint8x16_t a, uint8x16_t b, mve_pred16_t p) { return vminq_x (a, b, p); } -/* { dg-final { scan-assembler "vpst" } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_p_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_p_s16.c index 91bb63f6ba6..7c25c9d2f82 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_p_s16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_p_s16.c @@ -1,9 +1,20 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vminvt.s16 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) +** ... +*/ int16_t foo (int16_t a, int16x8_t b, mve_pred16_t p) { @@ -11,18 +22,20 @@ foo (int16_t a, int16x8_t b, mve_pred16_t p) } +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vminvt.s16 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) +** ... +*/ int16_t foo1 (int16_t a, int16x8_t b, mve_pred16_t p) { return vminvq_p (a, b, p); } - -int16_t -foo2 (int8_t a, int16x8_t b, mve_pred16_t p) -{ - return vminvq_p (a, b, p); -} - -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ -/* { dg-final { scan-assembler-times "vminvt.s16" 3 } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_p_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_p_s32.c index a846701312c..d5f7418af38 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_p_s32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_p_s32.c @@ -1,9 +1,20 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vminvt.s32 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) +** ... +*/ int32_t foo (int32_t a, int32x4_t b, mve_pred16_t p) { @@ -11,18 +22,20 @@ foo (int32_t a, int32x4_t b, mve_pred16_t p) } +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vminvt.s32 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) +** ... +*/ int32_t foo1 (int32_t a, int32x4_t b, mve_pred16_t p) { return vminvq_p (a, b, p); } - -int32_t -foo2 (int16_t a, int32x4_t b, mve_pred16_t p) -{ - return vminvq_p (a, b, p); -} - -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ -/* { dg-final { scan-assembler-times "vminvt.s32" 3 } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_p_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_p_s8.c index 716d414f3a7..6a42170fc19 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_p_s8.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_p_s8.c @@ -1,9 +1,20 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vminvt.s8 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) +** ... +*/ int8_t foo (int8_t a, int8x16_t b, mve_pred16_t p) { @@ -11,18 +22,20 @@ foo (int8_t a, int8x16_t b, mve_pred16_t p) } +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vminvt.s8 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) +** ... +*/ int8_t foo1 (int8_t a, int8x16_t b, mve_pred16_t p) { return vminvq_p (a, b, p); } - -int8_t -foo2 (int32_t a, int8x16_t b, mve_pred16_t p) -{ - return vminvq_p (a, b, p); -} - -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ -/* { dg-final { scan-assembler-times "vminvt.s8" 3 } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_p_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_p_u16.c index cc7f8fe8933..8f2f68fef84 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_p_u16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_p_u16.c @@ -1,9 +1,20 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vminvt.u16 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) +** ... +*/ uint16_t foo (uint16_t a, uint16x8_t b, mve_pred16_t p) { @@ -11,18 +22,36 @@ foo (uint16_t a, uint16x8_t b, mve_pred16_t p) } +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vminvt.u16 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) +** ... +*/ uint16_t foo1 (uint16_t a, uint16x8_t b, mve_pred16_t p) { return vminvq_p (a, b, p); } - +/* +**foo2: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vminvt.u16 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) +** ... +*/ uint16_t -foo2 (uint32_t a, uint16x8_t b, mve_pred16_t p) +foo2 (uint16x8_t b, mve_pred16_t p) { - return vminvq_p (a, b, p); + return vminvq_p (1, b, p); } -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ -/* { dg-final { scan-assembler-times "vminvt.u16" 3 } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_p_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_p_u32.c index 6bde0be29cc..9d14c39c1dc 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_p_u32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_p_u32.c @@ -1,9 +1,20 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vminvt.u32 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) +** ... +*/ uint32_t foo (uint32_t a, uint32x4_t b, mve_pred16_t p) { @@ -11,18 +22,36 @@ foo (uint32_t a, uint32x4_t b, mve_pred16_t p) } +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vminvt.u32 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) +** ... +*/ uint32_t foo1 (uint32_t a, uint32x4_t b, mve_pred16_t p) { return vminvq_p (a, b, p); } - +/* +**foo2: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vminvt.u32 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) +** ... +*/ uint32_t -foo2 (uint8_t a, uint32x4_t b, mve_pred16_t p) +foo2 (uint32x4_t b, mve_pred16_t p) { - return vminvq_p (a, b, p); + return vminvq_p (1, b, p); } -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ -/* { dg-final { scan-assembler-times "vminvt.u32" 3 } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_p_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_p_u8.c index bb894904f3c..4c1f4406852 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_p_u8.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_p_u8.c @@ -1,9 +1,20 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vminvt.u8 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) +** ... +*/ uint8_t foo (uint8_t a, uint8x16_t b, mve_pred16_t p) { @@ -11,18 +22,36 @@ foo (uint8_t a, uint8x16_t b, mve_pred16_t p) } +/* +**foo1: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vminvt.u8 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) +** ... +*/ uint8_t foo1 (uint8_t a, uint8x16_t b, mve_pred16_t p) { return vminvq_p (a, b, p); } - +/* +**foo2: +** ... +** vmsr p0, (?:ip|fp|r[0-9]+)(?: @.*|) +** ... +** vpst(?: @.*|) +** ... +** vminvt.u8 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) +** ... +*/ uint8_t -foo2 (uint16_t a, uint8x16_t b, mve_pred16_t p) +foo2 (uint8x16_t b, mve_pred16_t p) { - return vminvq_p (a, b, p); + return vminvq_p (1, b, p); } -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ -/* { dg-final { scan-assembler-times "vminvt.u8" 3 } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_s16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_s16.c index 6d589aa4a05..e3242c0aa4d 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_s16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_s16.c @@ -1,9 +1,16 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vminv.s16 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) +** ... +*/ int16_t foo (int16_t a, int16x8_t b) { @@ -11,17 +18,16 @@ foo (int16_t a, int16x8_t b) } +/* +**foo1: +** ... +** vminv.s16 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) +** ... +*/ int16_t foo1 (int16_t a, int16x8_t b) { return vminvq (a, b); } -int16_t -foo2 (int8_t a, int16x8_t b) -{ - return vminvq (a, b); -} - -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ -/* { dg-final { scan-assembler-times "vminv.s16" 3 } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_s32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_s32.c index 7c727d6d92b..1325b38411d 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_s32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_s32.c @@ -1,9 +1,16 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vminv.s32 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) +** ... +*/ int32_t foo (int32_t a, int32x4_t b) { @@ -11,17 +18,16 @@ foo (int32_t a, int32x4_t b) } +/* +**foo1: +** ... +** vminv.s32 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) +** ... +*/ int32_t foo1 (int32_t a, int32x4_t b) { return vminvq (a, b); } -int32_t -foo2 (int8_t a, int32x4_t b) -{ - return vminvq (a, b); -} - -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ -/* { dg-final { scan-assembler-times "vminv.s32" 3 } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_s8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_s8.c index 76309482fc5..81c14a8ac6b 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_s8.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_s8.c @@ -1,9 +1,16 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vminv.s8 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) +** ... +*/ int8_t foo (int8_t a, int8x16_t b) { @@ -11,17 +18,16 @@ foo (int8_t a, int8x16_t b) } +/* +**foo1: +** ... +** vminv.s8 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) +** ... +*/ int8_t foo1 (int8_t a, int8x16_t b) { return vminvq (a, b); } -int8_t -foo2 (int32_t a, int8x16_t b) -{ - return vminvq (a, b); -} - -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ -/* { dg-final { scan-assembler-times "vminv.s8" 3 } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_u16.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_u16.c index 698975f456c..4372ac62388 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_u16.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_u16.c @@ -1,9 +1,16 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vminv.u16 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) +** ... +*/ uint16_t foo (uint16_t a, uint16x8_t b) { @@ -11,18 +18,28 @@ foo (uint16_t a, uint16x8_t b) } +/* +**foo1: +** ... +** vminv.u16 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) +** ... +*/ uint16_t foo1 (uint16_t a, uint16x8_t b) { return vminvq (a, b); } - -uint8_t -foo2 (uint32_t a, uint16x8_t b) +/* +**foo2: +** ... +** vminv.u16 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) +** ... +*/ +uint16_t +foo2 (uint16x8_t b) { - return vminvq (a, b); + return vminvq (1, b); } -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ -/* { dg-final { scan-assembler-times "vminv.u16" 3 } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_u32.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_u32.c index 7489f81debf..aff3679f49d 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_u32.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_u32.c @@ -1,9 +1,16 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vminv.u32 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) +** ... +*/ uint32_t foo (uint32_t a, uint32x4_t b) { @@ -11,17 +18,28 @@ foo (uint32_t a, uint32x4_t b) } +/* +**foo1: +** ... +** vminv.u32 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) +** ... +*/ uint32_t foo1 (uint32_t a, uint32x4_t b) { return vminvq (a, b); } +/* +**foo2: +** ... +** vminv.u32 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) +** ... +*/ uint32_t -foo2 (uint16_t a, uint32x4_t b) +foo2 (uint32x4_t b) { - return vminvq (a, b); + return vminvq (1, b); } -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ -/* { dg-final { scan-assembler-times "vminv.u32" 3 } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_u8.c b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_u8.c index aa2b986d558..883e5f2d2c7 100644 --- a/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_u8.c +++ b/gcc/testsuite/gcc.target/arm/mve/intrinsics/vminvq_u8.c @@ -1,9 +1,16 @@ /* { dg-require-effective-target arm_v8_1m_mve_ok } */ /* { dg-add-options arm_v8_1m_mve } */ /* { dg-additional-options "-O2" } */ +/* { dg-final { check-function-bodies "**" "" } } */ #include "arm_mve.h" +/* +**foo: +** ... +** vminv.u8 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) +** ... +*/ uint8_t foo (uint8_t a, uint8x16_t b) { @@ -11,18 +18,28 @@ foo (uint8_t a, uint8x16_t b) } +/* +**foo1: +** ... +** vminv.u8 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) +** ... +*/ uint8_t foo1 (uint8_t a, uint8x16_t b) { return vminvq (a, b); } - -uint16_t -foo2 (uint32_t a, uint8x16_t b) +/* +**foo2: +** ... +** vminv.u8 (?:ip|fp|r[0-9]+), q[0-9]+(?: @.*|) +** ... +*/ +uint8_t +foo2 (uint8x16_t b) { - return vminvq (a, b); + return vminvq (1, b); } -/* { dg-final { scan-assembler-not "__ARM_undef" } } */ -/* { dg-final { scan-assembler-times "vminv.u8" 3 } } */ +/* { dg-final { scan-assembler-not "__ARM_undef" } } */ \ No newline at end of file