From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1118) id E6A7D3858D1E; Wed, 30 Nov 2022 18:45:44 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org E6A7D3858D1E DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1669833944; bh=hCaEvg5qzpF4uAn3ZLJrP6ZhA6F2HKZ5XlFyv47cmHY=; h=From:To:Subject:Date:From; b=pr8wrj5CDXQ4Jh/evAf/3I/K6kXaU1x36/KnuftSYykReJUH7lylXbJJz54ApVUF1 z2MIZLm33qh1F8qyveFvjwaCFJfFXsLilWmqfmUZo42Sr9N/gOoS0E6mUueni7xOwQ oCPQTF12eXiXO7KmptAwrSWZ2ajeJUbGetcaHd8k= MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="utf-8" From: John David Anglin To: gcc-cvs@gcc.gnu.org Subject: [gcc r10-11102] Fix addvdi3 and subvdi3 patterns X-Act-Checkin: gcc X-Git-Author: John David Anglin X-Git-Refname: refs/heads/releases/gcc-10 X-Git-Oldrev: ef70237843c7da4e45b0fe7c3cb81aceb9cd081e X-Git-Newrev: 2391ea007f291b12c6602b7fd71bb92b7c945752 Message-Id: <20221130184544.E6A7D3858D1E@sourceware.org> Date: Wed, 30 Nov 2022 18:45:44 +0000 (GMT) List-Id: https://gcc.gnu.org/g:2391ea007f291b12c6602b7fd71bb92b7c945752 commit r10-11102-g2391ea007f291b12c6602b7fd71bb92b7c945752 Author: John David Anglin Date: Wed Nov 30 18:40:10 2022 +0000 Fix addvdi3 and subvdi3 patterns While most PA 2.0 instructions support both 32 and 64-bit traps and conditions, the addi and subi instructions only support 32-bit traps and conditions. Thus, we need to force immediate operands to register operands on the 64-bit target and use the add/sub instructions which can trap on 64-bit signed overflow. 2022-11-30 John David Anglin gcc/ChangeLog: * config/pa/pa.md (addvdi3): Force operand 2 to a register. Remove "addi,tsv,*" instruction from unamed pattern. (subvdi3): Force operand 1 to a register. Remove "subi,tsv" instruction from from unamed pattern. Diff: --- gcc/config/pa/pa.md | 40 ++++++++++++++++++++++------------------ 1 file changed, 22 insertions(+), 18 deletions(-) diff --git a/gcc/config/pa/pa.md b/gcc/config/pa/pa.md index 1803c66cd21..770befc908b 100644 --- a/gcc/config/pa/pa.md +++ b/gcc/config/pa/pa.md @@ -5071,23 +5071,25 @@ (match_dup 2)))) (const_int 0))])] "" - "") + " +{ + if (TARGET_64BIT) + operands[2] = force_reg (DImode, operands[2]); +}") (define_insn "" - [(set (match_operand:DI 0 "register_operand" "=r,r") - (plus:DI (match_operand:DI 1 "reg_or_0_operand" "%rM,rM") - (match_operand:DI 2 "arith11_operand" "r,I"))) + [(set (match_operand:DI 0 "register_operand" "=r") + (plus:DI (match_operand:DI 1 "reg_or_0_operand" "%rM") + (match_operand:DI 2 "register_operand" "r"))) (trap_if (ne (plus:TI (sign_extend:TI (match_dup 1)) (sign_extend:TI (match_dup 2))) (sign_extend:TI (plus:DI (match_dup 1) (match_dup 2)))) (const_int 0))] "TARGET_64BIT" - "@ - add,tsv,* %2,%1,%0 - addi,tsv,* %2,%1,%0" - [(set_attr "type" "binary,binary") - (set_attr "length" "4,4")]) + "add,tsv,* %2,%1,%0" + [(set_attr "type" "binary") + (set_attr "length" "4")]) (define_insn "" [(set (match_operand:DI 0 "register_operand" "=r") @@ -5262,23 +5264,25 @@ (match_dup 2)))) (const_int 0))])] "" - "") + " +{ + if (TARGET_64BIT) + operands[1] = force_reg (DImode, operands[1]); +}") (define_insn "" - [(set (match_operand:DI 0 "register_operand" "=r,r") - (minus:DI (match_operand:DI 1 "arith11_operand" "r,I") - (match_operand:DI 2 "reg_or_0_operand" "rM,rM"))) + [(set (match_operand:DI 0 "register_operand" "=r") + (minus:DI (match_operand:DI 1 "register_operand" "r") + (match_operand:DI 2 "reg_or_0_operand" "rM"))) (trap_if (ne (minus:TI (sign_extend:TI (match_dup 1)) (sign_extend:TI (match_dup 2))) (sign_extend:TI (minus:DI (match_dup 1) (match_dup 2)))) (const_int 0))] "TARGET_64BIT" - "@ - {subo|sub,tsv} %1,%2,%0 - {subio|subi,tsv} %1,%2,%0" - [(set_attr "type" "binary,binary") - (set_attr "length" "4,4")]) + "sub,tsv,* %1,%2,%0" + [(set_attr "type" "binary") + (set_attr "length" "4")]) (define_insn "" [(set (match_operand:DI 0 "register_operand" "=r,&r")