From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 2140) id 2A5FD385B50C; Thu, 1 Dec 2022 07:39:53 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 2A5FD385B50C DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1669880393; bh=peB1G1ldcJKwWwqfZntRjBvw4mrx/0oObRQwSTMlSwM=; h=From:To:Subject:Date:From; b=fft1ILj5SLtkehysdDfnsx8Hv17AoXJTBu6kmLfgsbYlZ9M16XBLwhob4NPy1zcO5 Rl3J1PAQhw6SGYc98cmUnjBO0l9SF9lrBfHuOMrRXkNTe6Go9WH0/m/PBkOUM2e8FV OLXn6D01mVitUgjpg0n7irMkF0y8NUQlgQmC5CvA= Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit From: Alexandre Oliva To: gcc-cvs@gcc.gnu.org Subject: [gcc(refs/users/aoliva/heads/testme)] [testsuite] [riscv] skip ssa-sink-18.c X-Act-Checkin: gcc X-Git-Author: Alexandre Oliva X-Git-Refname: refs/users/aoliva/heads/testme X-Git-Oldrev: fdf23207fe3a69bc35ac13633b9b3a7ccf95eb73 X-Git-Newrev: 4028927b80f7cdc4edf438b39b2bf4028a9e5eff Message-Id: <20221201073953.2A5FD385B50C@sourceware.org> Date: Thu, 1 Dec 2022 07:39:53 +0000 (GMT) List-Id: https://gcc.gnu.org/g:4028927b80f7cdc4edf438b39b2bf4028a9e5eff commit 4028927b80f7cdc4edf438b39b2bf4028a9e5eff Author: Alexandre Oliva Date: Thu Dec 1 04:38:46 2022 -0300 [testsuite] [riscv] skip ssa-sink-18.c On riscv64, despite being lp64, we choose two IV candidates as on arm, which prevents some of the expected sinking. Add an xfail for it. for gcc/testsuite/ChangeLog * gcc.dg/tree-ssa/ssa-sink-18.c: xfail sink2 on riscv64. Change-Id: I2f4bacf3055a7dba52520280eac0ce52d19af5b2 TN: VB12-007 Diff: --- gcc/testsuite/gcc.dg/tree-ssa/ssa-sink-18.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/gcc/testsuite/gcc.dg/tree-ssa/ssa-sink-18.c b/gcc/testsuite/gcc.dg/tree-ssa/ssa-sink-18.c index 421c78eba50..9ac0fc6e4de 100644 --- a/gcc/testsuite/gcc.dg/tree-ssa/ssa-sink-18.c +++ b/gcc/testsuite/gcc.dg/tree-ssa/ssa-sink-18.c @@ -207,6 +207,9 @@ compute_on_bytes (uint8_t *in_data, int in_len, uint8_t *out_data, int out_len) from bb 31 to bb 33" When -m32, Power and X86 will sink 3 instructions, but arm ilp32 couldn't sink due to ivopts chooses two IV candidates instead of one, which is - expected, so this case is restricted to lp64 only so far. */ + expected, so this case is restricted to lp64 only so far. This different + ivopts choice affects riscv64 as well, probably because it also lacks + base+index addressing modes, so the ip[len] address computation can't be + made from the IV computation above. */ - /* { dg-final { scan-tree-dump-times "Sunk statements: 4" 1 "sink2" { target lp64 } } } */ + /* { dg-final { scan-tree-dump-times "Sunk statements: 4" 1 "sink2" { target lp64 xfail { riscv64-*-* } } } } */