From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1923) id 8EEF93858D32; Thu, 1 Dec 2022 13:23:00 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 8EEF93858D32 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1669900980; bh=Hkuo/YZW1hz2Rxpzk0evG+XuKQerf32x1KVg3J3ZrlI=; h=From:To:Subject:Date:From; b=Gfr9oRi1dENHPSLd2mDjIGWVYqaRVEwDA5saNZJLFfrDCn052kC/1/Gub1HfzD+B4 +K477lKSAB4DRHonokjsbBlYsIn7kifYChgCTL8l8gudVBgwRwSgsKgrHC8KBpVr9S NG5yYGT2CRM08FWWYp7tLVCS+hsbXszdqAVnEL/8= Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit From: Philipp Tomsich To: gcc-cvs@gcc.gnu.org Subject: [gcc/vrull/heads/for-upstream] (18 commits) Add new flag 'falign-arrays' X-Act-Checkin: gcc X-Git-Author: Philipp Tomsich X-Git-Refname: refs/vendors/vrull/heads/for-upstream X-Git-Oldrev: 19954801e11a8733d190ea5a03e65bc3c5c05f4f X-Git-Newrev: 85b75e273cf56a9fcd114987eb9eff150fa3010d Message-Id: <20221201132300.8EEF93858D32@sourceware.org> Date: Thu, 1 Dec 2022 13:23:00 +0000 (GMT) List-Id: The branch 'vrull/heads/for-upstream' was updated to point to: 85b75e273cf... Add new flag 'falign-arrays' It previously pointed to: 19954801e11... Add new flag 'falign-arrays' Diff: !!! WARNING: THE FOLLOWING COMMITS ARE NO LONGER ACCESSIBLE (LOST): ------------------------------------------------------------------- 1995480... Add new flag 'falign-arrays' c4548b8... riscv: Add support for str(n)cmp inline expansion 3e7bc4c... riscv: Add support for strlen inline expansion c58e424... riscv: Use by-pieces to do overlapping accesses in block_mo db2e8c8... riscv: Move riscv_block_move_loop to separate file 72b806c... riscv: Enable overlap-by-pieces via tune param d7378ac... riscv: bitmanip/zbb: Add prefix/postfix and enable visiblit f4fca6a... RISC-V: Use .p2align for code-alignment 09787e9... ifcvt: add if-conversion to conditional-zero instructions e4d96fa... RISC-V: Ventana-VT1 supports XVentanaCondOps 71b468d... RISC-V: Support immediates in XVentanaCondOps 7a87a85... RISC-V: Add instruction fusion (for ventana-vt1) 9d95637... RISC-V: Add basic support for the Ventana-VT1 core 95e8d5d... RISC-V: Recognize bexti in negated if-conversion 95fbae4... RISC-V: Recognize sign-extract + and cases for XVentanaCond 852dc40... RISC-V: Support noce_try_store_flag_mask as vt.maskc 01d2399... RISC-V: Generate vt.maskc on noce_try_store_flag_mask if d7568da... RISC-V: Recognize xventanacondops extension Summary of changes (added commits): ----------------------------------- 85b75e2... Add new flag 'falign-arrays' 64014fe... riscv: Add support for str(n)cmp inline expansion 630b7f6... riscv: Add support for strlen inline expansion 69da0a0... riscv: Use by-pieces to do overlapping accesses in block_mo caf45ba... riscv: Move riscv_block_move_loop to separate file bf45c8e... riscv: Enable overlap-by-pieces via tune param de66611... riscv: bitmanip/zbb: Add prefix/postfix and enable visiblit c16304a... RISC-V: Use .p2align for code-alignment 02055c4... ifcvt: add if-conversion to conditional-zero instructions bfb9bc3... RISC-V: Ventana-VT1 supports XVentanaCondOps 1b99fc3... RISC-V: Support immediates in XVentanaCondOps 07d79c2... RISC-V: Add instruction fusion (for ventana-vt1) 13b2130... RISC-V: Add basic support for the Ventana-VT1 core b927329... RISC-V: Recognize bexti in negated if-conversion 029a73a... RISC-V: Recognize sign-extract + and cases for XVentanaCond b6a9dbe... RISC-V: Support noce_try_store_flag_mask as vt.maskc efee69b... RISC-V: Generate vt.maskc on noce_try_store_flag_mask if 7684dea... RISC-V: Recognize xventanacondops extension