From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1923) id E316F385841E; Thu, 1 Dec 2022 13:23:25 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org E316F385841E DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1669901005; bh=D7TLQHzIWTU0RSq0mvLtCe63SBUif1TqDiEWiy+96s8=; h=From:To:Subject:Date:From; b=inQdKfNB4lTaVsvMO6u43r3L/CImqYMvB5mV17di1mT3adRHPPG9O0UMhVTKsmqH5 TACH6e0JhQNmdBs131dMfTSKqJb4e8y3pHYfoAEyl1MhvjLVhg8P8MIHFXHLsOielT a3XlnLZeid2nLgxpurH/mmDxXk2q3WivlfBAo/TY= Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit From: Philipp Tomsich To: gcc-cvs@gcc.gnu.org Subject: [gcc(refs/vendors/vrull/heads/for-upstream)] RISC-V: Recognize bexti in negated if-conversion X-Act-Checkin: gcc X-Git-Author: Philipp Tomsich X-Git-Refname: refs/vendors/vrull/heads/for-upstream X-Git-Oldrev: 029a73afbcacac6e0d4f7b330d78b3d38d9b3d43 X-Git-Newrev: b92732960e37956e3ee42f5be094dfcb9d77812f Message-Id: <20221201132325.E316F385841E@sourceware.org> Date: Thu, 1 Dec 2022 13:23:25 +0000 (GMT) List-Id: https://gcc.gnu.org/g:b92732960e37956e3ee42f5be094dfcb9d77812f commit b92732960e37956e3ee42f5be094dfcb9d77812f Author: Philipp Tomsich Date: Wed Mar 30 00:01:30 2022 +0200 RISC-V: Recognize bexti in negated if-conversion While the positive case "if ((bits >> SHAMT) & 1)" for SHAMT 0..10 can trigger conversion into efficient branchless sequences - with Zbs (bexti + neg + and) - with XVentanaCondOps (andi + vt.maskc) the inverted/negated case results in andi a5,a0,1024 seqz a5,a5 neg a5,a5 and a5,a5,a1 due to how the sequence presents to the combine pass. This adds an additional splitter to reassociate the polarity reversed case into bexti + addi, if Zbs is present. gcc/ChangeLog: * config/riscv/xventanacondops.md: Add split to reassociate "andi + seqz + neg" into "bexti + addi". Commit-changes: 2 - Removed spurious empty line at the end of xventanacondops.md. Diff: --- gcc/config/riscv/xventanacondops.md | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/gcc/config/riscv/xventanacondops.md b/gcc/config/riscv/xventanacondops.md index f2eb886659f..1e01fe1c6de 100644 --- a/gcc/config/riscv/xventanacondops.md +++ b/gcc/config/riscv/xventanacondops.md @@ -123,3 +123,13 @@ { operands[2] = GEN_INT(1 << UINTVAL(operands[2])); }) + +(define_split + [(set (match_operand:X 0 "register_operand") + (neg:X (eq:X (zero_extract:X (match_operand:X 1 "register_operand") + (const_int 1) + (match_operand 2 "immediate_operand")) + (const_int 0))))] + "!TARGET_XVENTANACONDOPS && TARGET_ZBS" + [(set (match_dup 0) (zero_extract:X (match_dup 1) (const_int 1) (match_dup 2))) + (set (match_dup 0) (plus:X (match_dup 0) (const_int -1)))])