From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 2093) id 9099F3858438; Thu, 1 Dec 2022 16:14:54 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 9099F3858438 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1669911294; bh=Nze6aZ27P40SKvuqMJpQ6w754koerheLoDH4dzAfu7Q=; h=From:To:Subject:Date:From; b=vkn73o13KlHWu71U/duWxo+J/yV8KCIx2eDxHyKB5gFEmy6lRDxKrx+Sazgw9d4le B1VZ089fCEtwmXtK9S/DHNvJrPrjzA115c6QlLvgB0KWCWNr8Ckuy73bd8QubAqi6b LZlA4x15kifmQeGXeJqteIM5WGSlbolNC5cH6Krw= MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="utf-8" From: Kito Cheng To: gcc-cvs@gcc.gnu.org Subject: [gcc r13-4449] RISC-V: Remove tail && mask policy operand for vmclr, vmset, vmld, vmst X-Act-Checkin: gcc X-Git-Author: Ju-Zhe Zhong X-Git-Refname: refs/heads/master X-Git-Oldrev: 3b16afeb3f6aacf64b9f9c50b7cb9805a9dfff63 X-Git-Newrev: c126e144d407bdc36c4204ab1b76b584b6514786 Message-Id: <20221201161454.9099F3858438@sourceware.org> Date: Thu, 1 Dec 2022 16:14:54 +0000 (GMT) List-Id: https://gcc.gnu.org/g:c126e144d407bdc36c4204ab1b76b584b6514786 commit r13-4449-gc126e144d407bdc36c4204ab1b76b584b6514786 Author: Ju-Zhe Zhong Date: Tue Nov 29 09:22:01 2022 +0800 RISC-V: Remove tail && mask policy operand for vmclr, vmset, vmld, vmst 1. vector.md: remove tail && mask policy operand for mask mode operations since we don't need them according to RVV ISA. 2. riscv-v.cc: adapt emit_pred_op for mask mode predicated mov since all RVV modes including vector integer mode && vector float mode && vector bool mode are all use emit_pred_op function. For vector integer mode && vector float mode, we have instruction like vle.v/vse.v that we need tail && mask policy. However, for vector bool mode, the instruction is vlm/vsm that we don't need tail && mask policy. So we add a condition here to add tail && mask policy operand during expand if it is not a vector bool modes. This patch is to cleanup the code and make it be consistent with RVV ISA. gcc/ChangeLog: * config/riscv/riscv-v.cc (emit_pred_op): Adapt for mask mode. * config/riscv/vector.md: Remove Tail && make policy operand for mask mode mov. Diff: --- gcc/config/riscv/riscv-v.cc | 3 ++- gcc/config/riscv/vector.md | 2 -- 2 files changed, 2 insertions(+), 3 deletions(-) diff --git a/gcc/config/riscv/riscv-v.cc b/gcc/config/riscv/riscv-v.cc index d54795694f1..4992ff2470c 100644 --- a/gcc/config/riscv/riscv-v.cc +++ b/gcc/config/riscv/riscv-v.cc @@ -136,7 +136,8 @@ emit_pred_op (unsigned icode, rtx dest, rtx src, machine_mode mask_mode) rtx vlmax = emit_vlmax_vsetvl (mode); e.add_input_operand (vlmax, Pmode); - e.add_policy_operand (TAIL_AGNOSTIC, MASK_AGNOSTIC); + if (GET_MODE_CLASS (mode) != MODE_VECTOR_BOOL) + e.add_policy_operand (TAIL_AGNOSTIC, MASK_AGNOSTIC); e.expand ((enum insn_code) icode, MEM_P (dest) || MEM_P (src)); } diff --git a/gcc/config/riscv/vector.md b/gcc/config/riscv/vector.md index a2f5a3eb69c..1b822184d27 100644 --- a/gcc/config/riscv/vector.md +++ b/gcc/config/riscv/vector.md @@ -593,8 +593,6 @@ (unspec:VB [(match_operand:VB 1 "vector_mask_operand" "Wc1, Wc1, Wc1, Wc1, Wc1") (match_operand 4 "vector_length_operand" " rK, rK, rK, rK, rK") - (match_operand 5 "const_int_operand" " i, i, i, i, i") - (match_operand 6 "const_int_operand" " i, i, i, i, i") (reg:SI VL_REGNUM) (reg:SI VTYPE_REGNUM)] UNSPEC_VPREDICATE) (match_operand:VB 3 "vector_move_operand" " m, vr, vr, Wc0, Wc1")