From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 2140) id 090913858434; Sat, 3 Dec 2022 07:33:09 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 090913858434 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1670052789; bh=mtqyPeyyc7zIICDUij/1XYb4rV6liODJAbh2FrWGT8g=; h=From:To:Subject:Date:From; b=ISXzKWyveay3+Xm3kjk+8GuT5EfWJLpT8o/2eaUue61zRsI03YF38bj9e7K2lk+bL gAjiX+PlvtZKnxosXGjUkfnZ1zyfmnpmTxp63crNEnCoouqAsy+Ubah4QPB5hm7NqI /6z4cpaBWPFhEc3ASOYZIalE9n8FVCDXxFX4AAAg= Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit From: Alexandre Oliva To: gcc-cvs@gcc.gnu.org Subject: [gcc(refs/users/aoliva/heads/testme)] [PR40457] [arm] expand SI-aligned movdi into pair of movsi X-Act-Checkin: gcc X-Git-Author: Alexandre Oliva X-Git-Refname: refs/users/aoliva/heads/testme X-Git-Oldrev: 328d9cf03dd2ad6c469478d2099f5eb16dbe617a X-Git-Newrev: ff44d83e0f3577412a333b2c4a82cf1806bdf3f9 Message-Id: <20221203073309.090913858434@sourceware.org> Date: Sat, 3 Dec 2022 07:33:09 +0000 (GMT) List-Id: https://gcc.gnu.org/g:ff44d83e0f3577412a333b2c4a82cf1806bdf3f9 commit ff44d83e0f3577412a333b2c4a82cf1806bdf3f9 Author: Alexandre Oliva Date: Fri Dec 2 03:28:06 2022 -0300 [PR40457] [arm] expand SI-aligned movdi into pair of movsi When expanding a misaligned DImode move, emit aligned SImode moves if the parts are sufficiently aligned. This enables neighboring stores to be peephole-combined into stm, as expected by the PR40457 testcase, even after SLP vectorizes the originally aligned SImode stores into a misaligned DImode store. for gcc/ChangeLog PR target/40457 * config/arm/arm.md (movmisaligndi): Prefer aligned SImode moves. Diff: --- gcc/config/arm/arm.md | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md index 69bf343fb0e..a9eb0299aa7 100644 --- a/gcc/config/arm/arm.md +++ b/gcc/config/arm/arm.md @@ -12783,8 +12783,16 @@ rtx hi_op0 = gen_highpart_mode (SImode, DImode, operands[0]); rtx hi_op1 = gen_highpart_mode (SImode, DImode, operands[1]); - emit_insn (gen_movmisalignsi (lo_op0, lo_op1)); - emit_insn (gen_movmisalignsi (hi_op0, hi_op1)); + if (aligned_operand (lo_op0, SImode) && aligned_operand (lo_op1, SImode)) + { + emit_move_insn (lo_op0, lo_op1); + emit_move_insn (hi_op0, hi_op1); + } + else + { + emit_insn (gen_movmisalignsi (lo_op0, lo_op1)); + emit_insn (gen_movmisalignsi (hi_op0, hi_op1)); + } DONE; })