[gcc r12-8961] aarch64: Specify that FEAT_MOPS sequences clobber CC

[Kyrylo Tkachov <ktkachov@gcc.gnu.org>]

https://gcc.gnu.org/g:d61d6c91b023adf22908c9071e4a6dffa317de2a

commit r12-8961-gd61d6c91b023adf22908c9071e4a6dffa317de2a
Author: Kyrylo Tkachov <kyrylo.tkachov@arm.com>
Date:   Wed Nov 30 17:38:16 2022 +0000

    aarch64: Specify that FEAT_MOPS sequences clobber CC
    
    According to the architecture pseudocode the FEAT_MOPS sequences overwrite the NZCV flags
    as par of their operation, so GCC needs to model that in the relevant RTL patterns.
    For the testcase:
    void g();
    void foo (int a, size_t N, char *__restrict__ in,
             char *__restrict__ out)
    {
      if (a != 3)
        __builtin_memcpy (out, in, N);
      if (a > 3)
        g ();
    }
    
    we will currently generate:
    foo:
            cmp     w0, 3
            bne     .L6
    .L1:
            ret
    .L6:
            cpyfp   [x3]!, [x2]!, x1!
            cpyfm   [x3]!, [x2]!, x1!
            cpyfe   [x3]!, [x2]!, x1!
            ble     .L1 // Flags reused after CPYF* sequence
            b       g
    
    This is wrong as the result of cmp needs to be recalculated after the MOPS sequence.
    With this patch we'll insert a "cmp w0, 3" before the ble, similar to what clang does.
    
    Bootstrapped and tested on aarch64-none-linux-gnu.
    Pushing to trunk and to the GCC 12 branch after some baking time.
    
    gcc/ChangeLog:
    
            * config/aarch64/aarch64.md (aarch64_cpymemdi): Specify clobber of CC reg.
            (*aarch64_cpymemdi): Likewise.
            (aarch64_movmemdi): Likewise.
            (aarch64_setmemdi): Likewise.
            (*aarch64_setmemdi): Likewise.
    
    gcc/testsuite/ChangeLog:
    
            * gcc.target/aarch64/mops_5.c: New test.
            * gcc.target/aarch64/mops_6.c: Likewise.
            * gcc.target/aarch64/mops_7.c: Likewise.
    
    (cherry picked from commit cbdffae5745327b0e5eb887afc512daf34b049b1)

Diff:
---
 gcc/config/aarch64/aarch64.md             |  5 +++++
 gcc/testsuite/gcc.target/aarch64/mops_5.c | 17 +++++++++++++++++
 gcc/testsuite/gcc.target/aarch64/mops_6.c | 17 +++++++++++++++++
 gcc/testsuite/gcc.target/aarch64/mops_7.c | 16 ++++++++++++++++
 4 files changed, 55 insertions(+)

diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md
index 34b8059b45b..7a04f45cacc 100644
--- a/gcc/config/aarch64/aarch64.md
+++ b/gcc/config/aarch64/aarch64.md
@@ -1586,6 +1586,7 @@
      [(set (match_operand 2) (const_int 0))
       (clobber (match_dup 3))
       (clobber (match_dup 4))
+      (clobber (reg:CC CC_REGNUM))
       (set (match_operand 0)
 	   (unspec:BLK [(match_operand 1) (match_dup 2)] UNSPEC_CPYMEM))])]
   "TARGET_MOPS"
@@ -1599,6 +1600,7 @@
   [(set (match_operand:DI 2 "register_operand" "+&r") (const_int 0))
    (clobber (match_operand:DI 0 "register_operand" "+&r"))
    (clobber (match_operand:DI 1 "register_operand" "+&r"))
+   (clobber (reg:CC CC_REGNUM))
    (set (mem:BLK (match_dup 0))
         (unspec:BLK [(mem:BLK (match_dup 1)) (match_dup 2)] UNSPEC_CPYMEM))]
   "TARGET_MOPS"
@@ -1629,6 +1631,7 @@
    (set (match_operand:DI 2 "register_operand" "+&r") (const_int 0))
    (clobber (match_operand:DI 0 "register_operand" "+&r"))
    (clobber (match_operand:DI 1 "register_operand" "+&r"))
+   (clobber (reg:CC CC_REGNUM))
    (set (mem:BLK (match_dup 0))
         (unspec:BLK [(mem:BLK (match_dup 1)) (match_dup 2)] UNSPEC_MOVMEM))])]
  "TARGET_MOPS"
@@ -1674,6 +1677,7 @@
   [(parallel
      [(set (match_operand 2) (const_int 0))
       (clobber (match_dup 3))
+      (clobber (reg:CC CC_REGNUM))
       (set (match_operand 0)
 	   (unspec:BLK [(match_operand 1)
 			(match_dup 2)] UNSPEC_SETMEM))])]
@@ -1686,6 +1690,7 @@
 (define_insn "*aarch64_setmemdi"
   [(set (match_operand:DI 2 "register_operand" "+&r") (const_int 0))
    (clobber (match_operand:DI 0 "register_operand" "+&r"))
+   (clobber (reg:CC CC_REGNUM))
    (set (mem:BLK (match_dup 0))
         (unspec:BLK [(match_operand:QI 1 "aarch64_reg_or_zero" "rZ")
 		     (match_dup 2)] UNSPEC_SETMEM))]
diff --git a/gcc/testsuite/gcc.target/aarch64/mops_5.c b/gcc/testsuite/gcc.target/aarch64/mops_5.c
new file mode 100644
index 00000000000..8a2626786eb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/mops_5.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=armv8.6-a+mops" } */
+
+#include <stddef.h>
+
+void g();
+void foo (int a, size_t N, char *__restrict__ in,
+         char *__restrict__ out)
+{
+  if (a != 3)
+    __builtin_memcpy (out, in, N);
+  if (a > 3)
+    g ();
+}
+
+/* { dg-final { scan-assembler-times {cmp\tw0, *} 2 } } */
+
diff --git a/gcc/testsuite/gcc.target/aarch64/mops_6.c b/gcc/testsuite/gcc.target/aarch64/mops_6.c
new file mode 100644
index 00000000000..c6c9a548351
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/mops_6.c
@@ -0,0 +1,17 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=armv8.6-a+mops" } */
+
+#include <stddef.h>
+
+void g();
+void foo (int a, size_t N, char *__restrict__ in,
+         char *__restrict__ out)
+{
+  if (a != 3)
+    __builtin_memmove (out, in, N);
+  if (a > 3)
+    g ();
+}
+
+/* { dg-final { scan-assembler-times {cmp\tw0, *} 2 } } */
+
diff --git a/gcc/testsuite/gcc.target/aarch64/mops_7.c b/gcc/testsuite/gcc.target/aarch64/mops_7.c
new file mode 100644
index 00000000000..79720ca164c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/mops_7.c
@@ -0,0 +1,16 @@
+/* { dg-do compile } */
+/* { dg-options "-O2 -march=armv8.6-a+mops" } */
+
+#include <stddef.h>
+
+void g();
+void foo (int a, size_t N, char *__restrict__ out)
+{
+  if (a != 3)
+    __builtin_memset (out, 0, N);
+  if (a > 3)
+    g ();
+}
+
+/* { dg-final { scan-assembler-times {cmp\tw0, *} 2 } } */
+