From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1984) id D9DBF383B686; Tue, 13 Dec 2022 18:04:49 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org D9DBF383B686 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1670954689; bh=2QlsaKUs0ZfukqdVU4kTV3kSy2FK3ohotgooMPNJIQ4=; h=From:To:Subject:Date:From; b=c443wWb7GOpE/oRUhsiX3OjOXx43letAtGQogRiez4yeqgMuM7GMeQNynK8cLfpzU HeTBdv+qhRxuBxqUh1SnejuqrifnIqrRwHaqbnI7/UlPgbmhfW30BaOcRaiCVNQjMt kwD1nCu+wl7FqkZWcSegj74Y8U9y5SK5GKjD9WU0= MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="utf-8" From: Tamar Christina To: gcc-cvs@gcc.gnu.org Subject: [gcc r13-4680] AArch64: Fix ILP32 tbranch X-Act-Checkin: gcc X-Git-Author: Tamar Christina X-Git-Refname: refs/heads/master X-Git-Oldrev: 33be3ee36a7e2c0be383ec01b5fbc9aef39568fd X-Git-Newrev: 69ec1e2065ac43eea44fdfa703cf027ce72a62da Message-Id: <20221213180449.D9DBF383B686@sourceware.org> Date: Tue, 13 Dec 2022 18:04:49 +0000 (GMT) List-Id: https://gcc.gnu.org/g:69ec1e2065ac43eea44fdfa703cf027ce72a62da commit r13-4680-g69ec1e2065ac43eea44fdfa703cf027ce72a62da Author: Tamar Christina Date: Tue Dec 13 18:01:15 2022 +0000 AArch64: Fix ILP32 tbranch the baremetal builds are currently broken because the shift ends up in the wrong representation if the mode is SImode and the shift amount if 31. To fix this create the rtx constant with an explicit mode so the backend passes know which representation it needs to take. gcc/ChangeLog: * config/aarch64/aarch64.md (tbranch_3): Use gen_int_mode. Diff: --- gcc/config/aarch64/aarch64.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md index d749c98eef6..6c27fb89e66 100644 --- a/gcc/config/aarch64/aarch64.md +++ b/gcc/config/aarch64/aarch64.md @@ -957,7 +957,7 @@ { rtx bitvalue = gen_reg_rtx (mode); rtx reg = gen_lowpart (mode, operands[0]); - rtx val = GEN_INT (1UL << UINTVAL (operands[1])); + rtx val = gen_int_mode (HOST_WIDE_INT_1U << UINTVAL (operands[1]), mode); emit_insn (gen_and3 (bitvalue, reg, val)); operands[1] = const0_rtx; operands[0] = aarch64_gen_compare_reg (, bitvalue,