From mboxrd@z Thu Jan  1 00:00:00 1970
Return-Path: <kito@sourceware.org>
Received: by sourceware.org (Postfix, from userid 2093)
	id 07EEE3A15AA2; Mon, 19 Dec 2022 07:58:46 +0000 (GMT)
DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 07EEE3A15AA2
DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org;
	s=default; t=1671436726;
	bh=sHqWNGadm0ne1NnBVi95tEyTy9IRzyBMLbKeDKC5H7M=;
	h=From:To:Subject:Date:From;
	b=J3+qmUenRxskZ4kHg7Li81UHI+4cMM6CeAYvbXnGCxriEZgtp9ks+/GQEr42apLyu
	 7yIUdstYoqZi1XkFJ2+FFac5KuLrxbmek+2UKzy29PPTHCqhv0DZ/khJ96D4RBj6+g
	 FWaot26FkynfkWGZQwmqHAj1YsH5NkmeadR9w8QM=
MIME-Version: 1.0
Content-Transfer-Encoding: 7bit
Content-Type: text/plain; charset="utf-8"
From: Kito Cheng <kito@gcc.gnu.org>
To: gcc-cvs@gcc.gnu.org
Subject: [gcc r13-4768] RISC-V: Fix RVV related testsuite
X-Act-Checkin: gcc
X-Git-Author: Kito Cheng <kito.cheng@sifive.com>
X-Git-Refname: refs/heads/master
X-Git-Oldrev: e2e154fe5bac0f62cc8bfe59165c742885490a79
X-Git-Newrev: e4337398620098f96a7680ce748c9da178514acf
Message-Id: <20221219075846.07EEE3A15AA2@sourceware.org>
Date: Mon, 19 Dec 2022 07:58:46 +0000 (GMT)
List-Id: <gcc-cvs.sourceware.org>

https://gcc.gnu.org/g:e4337398620098f96a7680ce748c9da178514acf

commit r13-4768-ge4337398620098f96a7680ce748c9da178514acf
Author: Kito Cheng <kito.cheng@sifive.com>
Date:   Sat Nov 5 17:01:02 2022 -0700

    RISC-V: Fix RVV related testsuite
    
    Use wrapper of riscv_vector.h for RVV related testcases,
    more detail see https://gcc.gnu.org/pipermail/gcc-patches/2022-October/603140.html
    
    gcc/testsuite/ChangeLog:
    
            * gcc.target/riscv/rvv/base/mov-1.c: Use double quotes to
            include riscv_vector.h rather than angle brackets.
            * gcc.target/riscv/rvv/base/mov-10.c: Ditto.
            * gcc.target/riscv/rvv/base/mov-11.c: Ditto.
            * gcc.target/riscv/rvv/base/mov-12.c: Ditto.
            * gcc.target/riscv/rvv/base/mov-13.c: Ditto.
            * gcc.target/riscv/rvv/base/mov-2.c: Ditto.
            * gcc.target/riscv/rvv/base/mov-3.c: Ditto.
            * gcc.target/riscv/rvv/base/mov-4.c: Ditto.
            * gcc.target/riscv/rvv/base/mov-5.c: Ditto.
            * gcc.target/riscv/rvv/base/mov-6.c: Ditto.
            * gcc.target/riscv/rvv/base/mov-7.c: Ditto.
            * gcc.target/riscv/rvv/base/mov-8.c: Ditto.
            * gcc.target/riscv/rvv/base/mov-9.c: Ditto.
            * gcc.target/riscv/rvv/base/vread_csr.c: Ditto.
            * gcc.target/riscv/rvv/base/vsetvl-1.c: Ditto.
            * gcc.target/riscv/rvv/base/vwrite_csr.c: Ditto.

Diff:
---
 gcc/testsuite/gcc.target/riscv/rvv/base/mov-1.c      | 2 +-
 gcc/testsuite/gcc.target/riscv/rvv/base/mov-10.c     | 2 +-
 gcc/testsuite/gcc.target/riscv/rvv/base/mov-11.c     | 2 +-
 gcc/testsuite/gcc.target/riscv/rvv/base/mov-12.c     | 2 +-
 gcc/testsuite/gcc.target/riscv/rvv/base/mov-13.c     | 2 +-
 gcc/testsuite/gcc.target/riscv/rvv/base/mov-2.c      | 2 +-
 gcc/testsuite/gcc.target/riscv/rvv/base/mov-3.c      | 2 +-
 gcc/testsuite/gcc.target/riscv/rvv/base/mov-4.c      | 2 +-
 gcc/testsuite/gcc.target/riscv/rvv/base/mov-5.c      | 2 +-
 gcc/testsuite/gcc.target/riscv/rvv/base/mov-6.c      | 2 +-
 gcc/testsuite/gcc.target/riscv/rvv/base/mov-7.c      | 2 +-
 gcc/testsuite/gcc.target/riscv/rvv/base/mov-8.c      | 2 +-
 gcc/testsuite/gcc.target/riscv/rvv/base/mov-9.c      | 2 +-
 gcc/testsuite/gcc.target/riscv/rvv/base/vread_csr.c  | 2 +-
 gcc/testsuite/gcc.target/riscv/rvv/base/vsetvl-1.c   | 2 +-
 gcc/testsuite/gcc.target/riscv/rvv/base/vwrite_csr.c | 2 +-
 16 files changed, 16 insertions(+), 16 deletions(-)

diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/mov-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/mov-1.c
index 6a235e308f9..cfc565b8922 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/mov-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/mov-1.c
@@ -2,7 +2,7 @@
 /* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */
 /* { dg-final { check-function-bodies "**" "" } } */
 
-#include <riscv_vector.h>
+#include "riscv_vector.h"
 
 /*
 ** mov1:
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/mov-10.c b/gcc/testsuite/gcc.target/riscv/rvv/base/mov-10.c
index 10aa8297c30..419f19d0184 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/mov-10.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/mov-10.c
@@ -2,7 +2,7 @@
 /* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
 /* { dg-final { check-function-bodies "**" "" } } */
 
-#include <riscv_vector.h> 
+#include "riscv_vector.h" 
 
 /*
 ** mov1:
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/mov-11.c b/gcc/testsuite/gcc.target/riscv/rvv/base/mov-11.c
index f8da5bb6b93..1bb159c7099 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/mov-11.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/mov-11.c
@@ -2,7 +2,7 @@
 /* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
 /* { dg-final { check-function-bodies "**" "" } } */
 
-#include <riscv_vector.h> 
+#include "riscv_vector.h" 
 
 /*
 ** mov1:
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/mov-12.c b/gcc/testsuite/gcc.target/riscv/rvv/base/mov-12.c
index 5b8ce40b62d..7886886e2f5 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/mov-12.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/mov-12.c
@@ -2,7 +2,7 @@
 /* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
 /* { dg-final { check-function-bodies "**" "" } } */
 
-#include <riscv_vector.h> 
+#include "riscv_vector.h" 
 
 /*
 ** mov14:
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/mov-13.c b/gcc/testsuite/gcc.target/riscv/rvv/base/mov-13.c
index 8c630f3bedb..9515e07eca1 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/mov-13.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/mov-13.c
@@ -1,7 +1,7 @@
 /* { dg-do compile } */
 /* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */
 
-#include <riscv_vector.h> 
+#include "riscv_vector.h" 
 
 void mov1 (int8_t *in, int8_t *out) 
 { 
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/mov-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/mov-2.c
index b9bdd515747..301607a2906 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/mov-2.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/mov-2.c
@@ -2,7 +2,7 @@
 /* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */
 /* { dg-final { check-function-bodies "**" "" } } */
 
-#include <riscv_vector.h>
+#include "riscv_vector.h"
 
 /*
 ** mov2:
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/mov-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/mov-3.c
index a7a89db2735..ea69ab2dbd5 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/mov-3.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/mov-3.c
@@ -2,7 +2,7 @@
 /* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */
 /* { dg-final { check-function-bodies "**" "" } } */
 
-#include <riscv_vector.h>
+#include "riscv_vector.h"
 
 /*
 ** mov3:
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/mov-4.c b/gcc/testsuite/gcc.target/riscv/rvv/base/mov-4.c
index e8cfb4b10b4..50bbd106692 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/mov-4.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/mov-4.c
@@ -2,7 +2,7 @@
 /* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */
 /* { dg-final { check-function-bodies "**" "" } } */
 
-#include <riscv_vector.h>
+#include "riscv_vector.h"
 
 /*
 ** mov4:
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/mov-5.c b/gcc/testsuite/gcc.target/riscv/rvv/base/mov-5.c
index 5ca232ba867..680b4f42842 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/mov-5.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/mov-5.c
@@ -2,7 +2,7 @@
 /* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */
 /* { dg-final { check-function-bodies "**" "" } } */
 
-#include <riscv_vector.h>
+#include "riscv_vector.h"
 
 /*
 ** mov3:
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/mov-6.c b/gcc/testsuite/gcc.target/riscv/rvv/base/mov-6.c
index 41fc73bb099..6348b38d9d7 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/mov-6.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/mov-6.c
@@ -2,7 +2,7 @@
 /* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */
 /* { dg-final { check-function-bodies "**" "" } } */
 
-#include <riscv_vector.h>
+#include "riscv_vector.h"
 
 /*
 ** mov4:
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/mov-7.c b/gcc/testsuite/gcc.target/riscv/rvv/base/mov-7.c
index d4636e0adfb..c60920a8847 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/mov-7.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/mov-7.c
@@ -1,7 +1,7 @@
 /* { dg-do compile } */
 /* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */
 
-#include <riscv_vector.h>
+#include "riscv_vector.h"
 
 /* This testcase is testing whether RISC-V define REGMODE_NATURAL_SIZE.  */
 void foo (int8_t *in, int8_t *out)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/mov-8.c b/gcc/testsuite/gcc.target/riscv/rvv/base/mov-8.c
index 9447b05899d..f2cb244473f 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/mov-8.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/mov-8.c
@@ -2,7 +2,7 @@
 /* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */
 /* { dg-final { check-function-bodies "**" "" } } */
 
-#include <riscv_vector.h>
+#include "riscv_vector.h"
 
 /*
 ** mov1:
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/mov-9.c b/gcc/testsuite/gcc.target/riscv/rvv/base/mov-9.c
index 6d39e3c0f4d..902d65eb503 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/mov-9.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/mov-9.c
@@ -2,7 +2,7 @@
 /* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns -fno-schedule-insns2" } */
 /* { dg-final { check-function-bodies "**" "" } } */
 
-#include <riscv_vector.h>
+#include "riscv_vector.h"
 
 /* Test tieable of RVV types with same LMUL.  */
 /*
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vread_csr.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vread_csr.c
index fa643c58785..69c9c1fa5ca 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/vread_csr.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vread_csr.c
@@ -2,7 +2,7 @@
 /* { dg-additional-options "-O3" } */
 /* { dg-skip-if "test intrinsic using rvv" { *-*-* } { "*" } { "-march=rv*v*zfh*" } } */
 
-#include <riscv_vector.h>
+#include "riscv_vector.h"
 
 unsigned long vread_csr_vstart(void) {
   return vread_csr(RVV_VSTART);
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vsetvl-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vsetvl-1.c
index 661f2c9170e..60d3b499719 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/vsetvl-1.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vsetvl-1.c
@@ -2,7 +2,7 @@
 /* { dg-options "-march=rv32gcv -mabi=ilp32d -O3" } */
 
 #include <stddef.h>
-#include <riscv_vector.h>
+#include "riscv_vector.h"
 
 size_t test_vsetvl_e8mf8_imm0()
 {
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vwrite_csr.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vwrite_csr.c
index e23da4b12ea..f9b4e8848df 100644
--- a/gcc/testsuite/gcc.target/riscv/rvv/base/vwrite_csr.c
+++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vwrite_csr.c
@@ -2,7 +2,7 @@
 /* { dg-additional-options "-O3" } */
 /* { dg-skip-if "test intrinsic using rvv" { *-*-* } { "*" } { "-march=rv*v*zfh*" } } */
 
-#include <riscv_vector.h>
+#include "riscv_vector.h"
 
 void vwrite_csr_vstart(unsigned long value) {
   vwrite_csr(RVV_VSTART, value);